IP Library › Granted Patent US 12,581,671
Granted Patent B2
US 12,581,671 · App. 18/135,327 · Granted Mar 17, 2026

Capacitor structure with two stacked conductive vias

Inventors: Pin-Jhu Li (New Taipei City, TW); Shih-Fan Kuan (Taoyuan City, TW)
Assignee: NANYA TECHNOLOGY CORPORATION
H10D1/682H01L23/5223H10D1/692H10B12/03H10B12/30
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Quick Facts
Patent No.
US 12,581,671
App. No.
18/135,327
Granted
Mar 17, 2026
Kind
B2
Abstract

A capacitor structure and a method of manufacturing a capacitor structure are provided. The capacitor structure includes a conductive via, an intermediate dielectric layer and a top electrode. The conductive via includes a neck portion located near a middle portion thereof. The intermediate dielectric layer is disposed on the conductive via. The top electrode is disposed on the intermediate dielectric layer.

Claims (29)

1 . A capacitor structure, comprising:

a conductive via including a neck portion located near a middle portion thereof;

an intermediate dielectric layer disposed on the conductive via;

a top electrode disposed on the intermediate dielectric layer;

a first support layer;

a second support layer disposed over the first support layer and defining an opening; and

a third support layer disposed over the second support layer and defining an opening;

wherein the neck portion of the conductive via has a tapered shape that a width thereof is gradually reduced away from the intermediate dielectric layer;

wherein the first support layer, the second support layer, and the third support layer are spaced apart from each other,

wherein the conductive via extends through the first support layer, the second support layer and the third support layer, wherein the intermediate dielectric layer covers a sidewall of the opening of the second support layer, a sidewall of the opening of the third support layer, and portions of the conductive via exposed from the first support layer, the second support layer and the third support layer.

2 . The capacitor structure of claim 1 , wherein the intermediate dielectric layer is conformal with the conductive via, and the top electrode is conformal with the intermediate dielectric layer.

3 . The capacitor structure of claim 1 , wherein the conductive via further includes a shoulder portion, and the neck portion connects to the shoulder portion to form a step structure, wherein the width of the neck portion is less than a width of the shoulder portion.

4 . The capacitor structure of claim 1 , further comprising a filling material and a first conductive layer attached to a bottom surface of the first support layer, wherein the conductive via is electrically connected to the first conductive layer, wherein the filling material is filled between a bottom surface of the first support layer and a top surface of the second support layer and between a bottom surface of the second support layer and a top surface of the third support layer.

5 . The capacitor structure of claim 1 , wherein the conductive via comprises:

a first conductive via disposed between the first support layer and the second support layer; and

a second conductive via disposed between the second support layer and the third support layer, and stacked on the first conductive via,

wherein an interface between the first conductive via and the second conductive via is substantially coplanar with a top surface of the second support layer;

wherein the first conductive via and the second conductive via are tapered toward the first support layer.

6 . The capacitor structure of claim 5 , wherein a top surface of the first conductive via includes the shoulder portion, and a lower portion of the second conductive via includes the neck portion.

7 . The capacitor structure of claim 5 , wherein a lateral surface of the entire first conductive via has a substantially consistent slope, and a lateral surface of the entire second conductive via has a substantially consistent slope.

8 . The capacitor structure of claim 7 , wherein the slope of the lateral surface of the first conductive via is equal to or different from the slope of the lateral surface of the second conductive via.

9 . The capacitor structure of claim 1 , wherein the conductive via comprises:

a first conductive via; and

a second conductive via stacked on the first conductive via,

wherein an interface is between the first conductive via and the second conductive via;

wherein the first conductive via and the second conductive via are tapered.

10 . The capacitor structure of claim 9 , wherein a top surface of the first conductive via includes the shoulder portion, and a lower portion of the second conductive via includes the neck portion.

11 . The capacitor structure of claim 9 , wherein an upper portion of the second conductive via defines an indentation portion, wherein the indentation portion of the second conductive via is formed at one of lateral surfaces thereof.

12 . The capacitor structure of claim 11 , wherein the intermediate dielectric layer covers the indentation portion of the second conductive via.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 17, 2023
From: LI, PIN-JHU; KUAN, SHIH-FAN
To: NANYA TECHNOLOGY CORPORATION
Reel/Frame 063344/0194 →
Continuity (1)
Related Publication 20240347580A1 · Oct 17, 2024
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