Schottky diode and method for forming the same
A Schottky diode includes a substrate, a first drift region in the substrate, a second drift region in the substrate, a first dielectric layer disposed over the substrate, a first doped region in the first drift region, a second doped region in the second drift region, a third doped region in the first drift region, and a metal field plate disposed over the first dielectric layer. The first drift region and the first doped region include a first conductivity type. The second drift region, the second doped region and third doped region include a second conductivity type complementary to the first conductivity type. The first dielectric layer overlaps a portion of the first drift region and a portion of the second drift region. The second doped region is separated from the first doped region.
1 . A method for forming a Schottky diode, comprising:
forming a first buried layer and a second buried layer in a substrate, wherein the first buried layer comprises a first conductivity type, and the second buried layer comprises a second conductivity type complementary to the first conductivity type;
forming a first drift region comprising the first conductivity type and a second drift region comprising the second conductivity type in the substrate and over the first buried layer and the second buried layer;
forming a first doped region, comprising the first conductivity type, in the first drift region; a second doped region, comprising the second conductivity type, in the second drift region; and a third doped region, comprising the second conductivity type, in the first drift region;
forming an isolation structure over the substrate, wherein the forming of the isolation structure further comprises:
forming a first dielectric layer on the substrate; and
forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer is in contact with a top surface and sidewalls of the first dielectric layer and the substrate; and
forming a metal field plate over the isolation structure.
2 . The method of claim 1 , further comprising forming a first silicide layer over the first doped region and a second silicide layer over the second and third doped regions.
3 . The method of claim 1 , wherein the forming of the metal field plate further comprises:
forming a metal layer over the substrate;
forming a third dielectric layer over the metal layer; and
patterning the third dielectric layer and the metal layer to form the metal field plate over the isolation structure and a patterned third dielectric layer over the metal field plate.
4 . The method of claim 1 , further comprising:
forming a dielectric structure over the substrate; and
forming a first connecting plug electrically connected to the first doped region, a second connecting plug electrically connected to the second doped region and the third doped regions, and a third connecting plug electrically connected to the metal field plate.
5 . The method of claim 1 , wherein a concentration of the second doped region and a concentration of the third doped region are equal.
6 . The method of claim 4 , wherein the forming of the dielectric structure further comprising forming an etch stop layer and forming an interlayer dielectric (ILD) over the etch stop layer.
7 . A method for forming a semiconductor structure including a Schottky diode, comprising:
receiving a substrate having a first region and a second region;
forming a first buried layer and a second buried layer in the first region and forming a well region in the second region;
forming a first drift region and a second drift region in the first region;
forming a gate structure in the second region;
forming a plurality of doped regions in the first region and a source/drain region in the second region;
forming a first dielectric layer in the first region;
forming a metal layer over the first dielectric layer;
forming a second dielectric layer over the metal layer; and
patterning the second dielectric layer and the metal layer to form a metal field plate over the first dielectric layer and a patterned second dielectric layer over the metal field plate.
8 . The method of claim 7 , further comprising forming a plurality of first silicide layers over the doped regions in the first region and a second silicide layer over the source/drain region in the second region.
9 . The method of claim 7 , wherein the doped regions comprise:
a first doped region in the first drift region;
a second doped region in the second drift region; and
a third doped region in the first drift region,
wherein the first buried layer, the first drift region and the first doped region comprise a first conductivity type, and the second buried layer, the second drift region, the second doped region and the third doped region comprise a second conductivity type complementary to the first conductivity type.
10 . The method of claim 7 , wherein a width of the metal field plate in the first region is equal to or less than a width of the first dielectric layer in the first region.
11 . The method of claim 7 , further comprising:
forming a dielectric structure over the substrate; and
forming a plurality of first connecting plugs electrically connected to the doped regions, and a second connecting plug electrically connected to the metal field plate.
12 . The method of claim 11 , further comprising forming a third connecting plug electrically connected to the gate structure.
13 . A method for forming a semiconductor structure including a Schottky diode, comprising:
receiving a substrate having a first region and a second region;
forming a first buried layer and a second buried layer in the first region;
forming a first drift region and a second drift region in the first region;
forming a gate structure in the second region;
forming a plurality of doped regions in the first region and a source/drain region in the second region;
forming a first dielectric layer in the first region and a second dielectric layer in the second region, wherein the second dielectric layer covers a portion of the gate structure and a portion of the source/drain region; and
forming a first metal field plate over the first dielectric layer and a second metal field plate over the second dielectric layer.
14 . The method of claim 13 , wherein the doped regions comprise:
a first doped region in the first drift region;
a second doped region in the second drift region; and
a third doped region in the first drift region,
wherein the first buried layer, the first drift region and the first doped region comprise a first conductivity type, and the second buried layer, the second drift region, the second doped region and the third doped region comprise a second conductivity type complementary to the first conductivity type.
15 . The method of claim 13 , further comprising forming a plurality of first silicide layers over the doped regions in the first region, and a second silicide layer over the source/drain region in the second region.
16 . The method of claim 13 , wherein a width of the first metal field plate is equal to or less than a width of the first dielectric layer.
17 . The method of claim 13 , wherein a width of the second metal field plate is equal to or less than a width of the second dielectric layer.
18 . The method of claim 13 , further comprising:
forming a dielectric structure over the substrate; and
forming a plurality of first connecting plugs electrically connected to the doped regions, and a second connecting plug electrically connected to the first metal field plate.
19 . The method of claim 18 , further comprising forming a third connecting plug electrically connected to the source/drain region, and a fourth connecting plug electrically connected to the second metal field plate.
20 . The method of claim 13 , wherein the forming of the first metal field plate and the second metal field plate further comprises:
forming a third dielectric layer over the first dielectric layer, the second dielectric layer and the gate structure;
forming a metal layer over the third dielectric layer; and
removing portions of the metal layer to form the first metal field plate and the second metal field plate, and to expose the third dielectric layer.