Via alternate net spacing
A chip includes a first net, and a second net, wherein the first net and the second net are formed from a same metal layer, and the second net neighbors the first net. The chip also includes first vias disposed on the first net, and second vias disposed on the second net. A first spacing is greater than a second spacing, the first spacing is between a first one of the first vias and a second one of the first vias, the first one of the first vias and the second one of the first vias are adjacent, and the second spacing is between the first one of the first vias and one of the second vias closest to the first one of the first vias.
1 . A chip, comprising:
a first net;
a second net, wherein the first net and the second net are formed from a same metal layer, and the second net neighbors the first net;
first vias disposed on the first net;
second vias disposed on the second net;
a third net, wherein the third net is formed from the same metal layer as the first net and the second net, and the third net neighbors the second net; and
third vias disposed on the third net;
wherein a first spacing is greater than a second spacing, the first spacing is between a first one of the first vias and a second one of the first vias, the first one of the first vias and the second one of the first vias are adjacent, and the second spacing is between the first one of the first vias and one of the second vias closest to the first one of the first vias; and
wherein a third spacing is greater than a fourth spacing, the third spacing is between a first one of the third vias and a second one of the third vias, the first one of the third vias and the second one of the third vias are adjacent, and the fourth spacing is between the first one of the third vias and one of the second vias closest to the first one of the third vias.
2 . The chip of claim 1 , wherein the first spacing is greater than 1.1 times a minimum spacing specified by a design rule.
3 . The chip of claim 2 , wherein the second spacing is within a range of the minimum spacing to 1.1 times the minimum spacing.
4 . The chip of claim 1 , wherein the first spacing is greater than 1.3 times a minimum spacing specified by a design rule.
5 . The chip of claim 1 , wherein the first spacing is greater than 1.5 times a minimum spacing specified by a design rule.
6 . The chip of claim 1 , wherein a ratio of the first spacing to the second spacing is greater than 1.1.
7 . The chip of claim 1 , wherein a ratio of the first spacing to the second spacing is greater than 1.3.
8 . The chip of claim 1 , wherein a ratio of the first spacing to the second spacing is greater than 1.5.
9 . The chip of claim 1 , wherein the first net comprises a first contiguous metal line and the second net comprises a second contiguous metal line.
10 . The chip of claim 1 , wherein:
the first net is electrically coupled to a source or a drain of a transistor; and
the second net is electrically coupled to a gate of the transistor.
11 . The chip of claim 1 , wherein:
the first net is electrically coupled to a drain of a transistor;
the second net is electrically coupled to a gate of the transistor; and
the third net is electrically coupled to a source of the transistor.
12 . The chip of claim 1 , wherein the first spacing and the third spacing are each greater than 1.1 times a minimum spacing specified by a design rule.
13 . The chip of claim 1 , wherein the first spacing and the third spacing are each greater than 1.3 times a minimum spacing specified by a design rule.
14 . The chip of claim 1 , wherein the first spacing and the third spacing are each greater than 1.5 times a minimum spacing specified by a design rule.