Etch monitoring and performing
In a method of patterning an integrated circuit, test layer thickness variation data is received when a test layer with a known thickness disposed over a test substrate undergoes tilted angle plasma etching. Overlay offset data per substrate locations caused by the tilted angle plasma etching is determined. The overlay offset data is determined based on the received thickness variation data. The overlay offset data is associated with an overlay between first circuit patterns of a first layer on the semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the substrate. A location of the substrate is adjusted based on the overlay offset data during a lithography operation to pattern a resist layer over the second layer. The second layer is patterned based on the projected layout patterns of the reticle and using the tilted angle plasma etching.
1 . A system for producing a semiconductor device, comprising:
a main controller;
an analyzer module coupled to the main controller;
a plasma etching device that comprises:
a plasma beam generator configured to generate a plasma beam;
an etching chamber;
a stage configured to hold a substrate in the etching chamber;
a flow rate controller coupled to the plasma beam generator; and
an etch control circuit coupled to the plasma beam generator and configured to induce a tilted angle to the plasma beam; and
an exposure device that comprises:
a reflective reticle;
a stage coupled to a stage controller, wherein the stage controller is coupled to the main controller;
a substrate with a photo resist layer disposed on the substrate;
a radiation source configured to generate a radiation beam;
an illumination optical system comprising one or more first optical components configured to project the radiation beam on the reflective reticle; and
a projection optical system comprising one or more second optical components configured to project a reflected radiation beam from the reflective reticle onto the photo resist layer of the substrate,
wherein the analyzer module is configured to receive overlay offset data per semiconductor substrate locations caused by the tilted angle plasma etching, wherein the overlay offset data is determined based on received thickness variation data when a uniform thickness semiconductor layer undergoes the tilted angle plasma etching for a predetermined amount of time, and wherein the overlay offset data is associated with an overlay between first circuit patterns of a first layer on a semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the semiconductor substrate.
2 . The system of claim 1 , wherein the etch control circuit is configured to apply an electric filed or to apply a magnetic field to the plasma beam to induce the tilted angle to the plasma beam.
3 . The system of claim 1 , the plasma etching device further comprising:
a film thickness measurement device, wherein the plasma etching device is configured to perform the tilted angle plasma etching on the uniform thickness semiconductor layer disposed on a test wafer for the predetermined amount of time, wherein the film thickness measurement device is configured to measure thickness values of a remaining semiconductor layer on the test wafer and send the measured thickness values to the analyzer module, and wherein the analyzer module is configured to determine the overlay offset data per semiconductor substrate locations based on the measured thickness values.
4 . The system of claim 1 , wherein the main controller is configured to:
receive the overlay offset data per semiconductor substrate locations from the analyzer module; and
send the overlay offset data per semiconductor substrate locations to the stage controller of the exposure device; and
command the stage controller of the exposure device to move the stage by overlay offset data before turning on the radiation source to project layout patterns of the reflective reticle on the photo resist layer of the substrate.
5 . The system of claim 4 , wherein the exposure device further comprises:
a radiation controller coupled to the radiation source, wherein the main controller is configured to:
command the radiation controller to adjust an amount of time the radiation source is turned on to adjust a projection energy for imaging the layout patterns of the reflective reticle on the photo resist layer of the substrate.
6 . The system of claim 4 , wherein the flow rate controller of the plasma etching device is coupled to the main controller and the main controller is configured to command the flow rate controller to adjust an intensity of the plasma beam.
7 . A system for producing a semiconductor device, comprising:
a main controller;
an analyzer module coupled to the main controller; and
a plasma etching device that comprises:
a plasma beam generator configured to generate a plasma beam;
an etching chamber;
a first stage configured to hold a substrate in the etching chamber;
a flow rate controller coupled to the plasma beam generator; and
an etch control circuit coupled to the plasma beam generator and configured to induce a tilted angle to the plasma beam;
wherein the analyzer module is configured to receive overlay offset data per semiconductor substrate locations caused by the tilted angle plasma etching,
wherein the overlay offset data is determined based on received thickness variation data when a uniform thickness semiconductor layer undergoes the tilted angle plasma etching for a predetermined amount of time, and
wherein the overlay offset data is associated with an overlay between first circuit patterns of a first layer on a semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the semiconductor substrate.
8 . The system of claim 7 , further comprising:
an exposure device that comprises:
a reflective reticle;
a second stage coupled to a stage controller to hold the substrate with a photo resist layer disposed on the substrate, wherein the stage controller is coupled to the main controller;
a radiation source configured to generate a radiation beam;
an illumination optical system comprising one or more first optical components configured to project the radiation beam on the reflective reticle; and
a projection optical system comprising one or more second optical components configured to project a reflected radiation beam from the reflective reticle onto the photo resist layer of the substrate.
9 . The system of claim 8 , wherein the main controller is configured to:
receive the overlay offset data per semiconductor substrate locations from the analyzer module;
send the overlay offset data per semiconductor substrate locations to the stage controller of the exposure device; and
command the stage controller of the exposure device to move the stage by overlay offset data before turning on the radiation source to project layout patterns of the reflective reticle on the photo resist layer of the substrate.
10 . The system of claim 9 , wherein the exposure device further comprises a radiation controller coupled to the radiation source, wherein the main controller is configured to command the radiation controller to adjust an amount of time the radiation source is turned on to adjust a projection energy for imaging the layout patterns of the reflective reticle on the photo resist layer of the substrate.
11 . The system of claim 7 , wherein the etch control circuit is configured to apply an electric filed to the plasma beam to induce the tilted angle to the plasma beam.
12 . The system of claim 7 , wherein the etch control circuit is configured to apply a magnetic field to the plasma beam to induce the tilted angle to the plasma beam.
13 . The system of claim 7 , wherein the flow rate controller of the plasma etching device is coupled to the main controller, and wherein the main controller is configured to command the flow rate controller to adjust an intensity of the plasma beam.
14 . The system of claim 7 , the plasma etching device further comprising a film thickness measurement device, wherein the plasma etching device is configured to perform the tilted angle plasma etching on the uniform thickness semiconductor layer disposed on a test wafer for the predetermined amount of time.
15 . The system of claim 14 , wherein the film thickness measurement device is configured to measure thickness values of a remaining semiconductor layer on the test wafer and send the measured thickness values to the analyzer module.
16 . The system of claim 15 , wherein the analyzer module is configured to determine the overlay offset data per semiconductor substrate locations based on the measured thickness values.
17 . A plasma etching device, comprising: a plasma beam generator configured to generate a plasma beam; an etching chamber; a stage coupled to a stage controller, the stage configured to hold a substrate in the etching chamber; and a flow rate controller coupled to the plasma beam generator, wherein the plasma beam generator is coupled to and controlled by an etch control circuit to induce a tilted angle to the plasma beam, wherein overlay offset data per semiconductor substrate locations caused by the tilted angle plasma etching is received by an analyzer module, and wherein the overlay offset data is associated with an overlay between first circuit patterns of a first layer on the substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the substrate.
18 . The plasma etching device of claim 17 , wherein the overlay offset data is determined based on received thickness variation data when a uniform thickness semiconductor layer undergoes the tilted angle plasma etching for a predetermined amount of time.
19 . The plasma etching device of claim 17 , wherein the etch control circuit is configured to apply an electric filed or a magnetic field to the plasma beam to induce the tilted angle to the plasma beam.
20 . The plasma etching device of claim 17 , wherein the stage controller is configured to adjust a location of the substrate based on the overlay offset data during a lithography operation to pattern a resist layer over the second layer by projecting layout patterns of a reticle corresponding to the second circuit patterns onto the resist layer.