Circuit board and semiconductor package board comprising same
A circuit board according to an embodiment includes an insulating layer; a circuit pattern disposed on the insulating layer, and a first protective layer disposed on the insulating layer, wherein the first protective layer includes a first opening vertically overlapping at least a part of an upper surface of the circuit pattern; wherein an inner wall of the first protective layer constituting the first opening includes: a first portion having a first inclination, and a second portion disposed on the first portion and having a second inclination different from the first inclination, and wherein the first portion overlaps the circuit pattern in a horizontal direction.
1 . A circuit board comprising:
an insulating layer;
a circuit pattern disposed on the insulating layer; and
a first protective layer disposed on the insulating layer having a first opening overlapping the circuit pattern in a vertical direction,
wherein an inner wall of the first opening of the first protective layer includes:
a first portion connected to a lower surface of the first protective layer and overlapping the circuit pattern in a horizontal direction; and
a second portion provided between an upper surface of the first protective layer and the first portion and not overlapping with the circuit pattern in the horizontal direction;
wherein the first portion has a first inclination, and the second portion has a second inclination different from the first inclination, and
wherein the second portion has a curved surface having a first curvature.
2 . The circuit board of claim 1 , wherein the first portion is perpendicular to the lower surface of the first protective layer.
3 . The circuit board of claim 1 , wherein a surface roughness of the first portion of the first protective layer is different from a surface roughness of the second portion of the first protective layer.
4 . The circuit board of claim 1 , wherein a height of a boundary between the first portion and the second portion is higher than or equal to a height of the circuit pattern.
5 . The circuit board of claim 1 , further comprising:
a second protective layer disposed on the first protective layer,
wherein the second protective layer includes a second opening vertically overlapping the first opening.
6 . The circuit board of claim 5 , wherein a width of the second opening is greater than a width of the first opening.
7 . The circuit board of claim 5 , wherein an inner wall of the second opening of the second protective layer includes a third portion having a third inclination different from the first inclination and the second inclination of the first portion and the second portion of the first protective layer.
8 . The circuit board of claim 7 , wherein the third portion is a curved surface having a second curvature different from the first curvature of the second portion.
9 . The circuit board of claim 8 , wherein the second curvature is greater than the first curvature.
10 . The circuit board of claim 7 , wherein the third portion does not overlap with the first portion in a vertical direction.
11 . The circuit board of claim 10 , wherein the third portion does not overlap with the second portion in a vertical direction.
12 . The circuit board of claim 1 , wherein the circuit pattern includes a plurality of pads, and
wherein the plurality of pads are overlapped with the first opening in the vertical direction and spaced apart from each other in the horizontal direction.
13 . A semiconductor package comprising:
an insulating layer;
a plurality of pads disposed on the insulating layer and spaced apart from each other in a horizontal direction;
a first protective layer disposed on the insulating layer and having a first opening overlapping the plurality of pads in a vertical direction;
a contacting portion disposed on the plurality of pads;
a semiconductor device disposed on the contacting portion; and
a molding layer for molding the semiconductor device;
wherein an inner wall of the first opening of the first protective layer includes:
a first portion connected to a lower surface of the first protective layer and overlapping a circuit pattern in a horizontal direction; and
a second portion provided between an upper surface of the first protective layer and the first portion and not overlapping with the circuit pattern in the horizontal direction;
wherein the first portion has a first inclination, and the second portion has a second inclination different from the first inclination,
wherein the second portion has a curved surface having a first curvature; and
wherein the molding layer is provided covering the first and second portions.
14 . The semiconductor package of claim 13 , wherein a surface roughness of the first portion of the first protective layer is different from a surface roughness of the second portion of the first protective layer.
15 . The semiconductor package of claim 13 , wherein a height of a boundary between the first portion and the second portion is higher than or equal to a height of each of the plurality of pads.
16 . The semiconductor package of claim 13 , further comprising:
a second protective layer disposed on the first protective layer,
wherein the second protective layer includes a second opening vertically overlapping the first opening, and
wherein the molding layer is provided covering an inner wall of the second opening.
17 . The semiconductor package of claim 16 , wherein a width of the second opening is greater than a width of the first opening, and
wherein the inner wall of the second opening of the second protective layer includes a third portion having a third inclination different from the first inclination and the second inclination of the first portion and the second portion of the first protective layer.
18 . The semiconductor package of claim 17 , wherein the third portion is a curved surface having a second curvature different from the first curvature of the second portion.
19 . The semiconductor package of claim 18 , wherein the second curvature is greater than the first curvature.
20 . The semiconductor package of claim 17 , wherein the third portion does not overlap with the first portion in a vertical direction.