Compiler for neural accelerator
A compiler of a computing device is described that identifies a sequence of neural network models frequently invoked by an application of the computing device, compiles the models in that sequence, and loads a static random access memory (SRAM) of a hardware accelerator with the compiled models only when the same compiled models—from another, but same, sequence that was previously invoked—are not already present in the SRAM. This prevents unnecessary reloading of compiled models into the SRAM, thereby increasing runtime speed and conserving computational energy.
1 . A computer-implemented method comprising:
identifying a first set of neural network models that have been executed on a hardware accelerator of a computing device more than a threshold number of times in a preset amount of time in the past;
identifying a sequence in which the first set of models were executed on the hardware accelerator;
compiling each neural network model of the first set of neural network models in the sequence for execution by the hardware accelerator and assigning a first hash to the identified sequence of models;
outputting, for each neural network model of the first set of neural network models in the sequence, the compiled model to the hardware accelerator for storage in one or more memories of the hardware accelerator,
compiling a second sequence of neural network models and computing a second hash for the second sequence of neural network models;
determining that the first hash matches the second hash; and
in response, bypassing loading compiled models in the second sequence of neural network models into storage of the hardware accelerator.
2 . The method of claim 1 , further comprising:
receiving, for each neural network model of the first set of neural network models, a data structure including parameters of the neural network model,
wherein the compiling further comprises compiling the data structure for each neural network model of the first set of neural network models to generate a compiled data structure for each neural network model of the first set of neural network models, the compiled data structure being the compiled model.
3 . The method of claim 1 , further comprising:
assigning the same first hash to each compiled model in the identified sequence of models;
outputting the first hash along with each compiled model in the sequence to the hardware accelerator for storage in the one or more memories of the hardware accelerator;
assigning the same second hash to each compiled model in the previously compiled sequence of models, the second hash being same as the first hash when the second sequence is same as the first sequence, the second hash being different from the first hash when the second sequence is different from the first sequence,
wherein:
if the second hash is different from the first hash, the hardware accelerator is configured to replace each compiled model in the first sequence in the one or more memories with each compiled model in the second sequence in the one or more memories;
if the second hash is same as the first hash, the hardware accelerator is configured to prevent erasing each compiled model in the first sequence from the one or more memories.
4 . The method of claim 1 , wherein each of the first set of neural network models has been processed on the hardware accelerator more than five times in the past.
5 . The method of claim 4 , wherein the compiler compiles the first set of neural network models while the hardware accelerator simultaneously performs neural network computations of other one or more neural network models.
6 . The method of claim 1 , further comprising:
updating the identification of the first set of models and the identification of the sequence after preset intervals of time.
7 . The method of claim 6 , further comprising:
abstaining, for a preset time, from the updating in response to a failure of the compilation of the first set of neural network models.
8 . The method of claim 7 , wherein the abstaining comprises:
abstaining, for 7500 milliseconds, from the updating in response to the failure of the compilation of the first set of neural network models.
9 . The method of claim 1 , wherein the compiling of the first set of neural network models comprises:
determining that each neural network model within the first set of neural network models has a particular size that is compatible for the compiling.
10 . The device of claim 1 , wherein the compiling of the first set of neural network models comprises:
compiling only a single neural network model at any time.
11 . The method of claim 1 , wherein the sequence comprises a face recognition neural network model and one or more dependent neural network models that are to be processed after processing the face recognition neural network model.
12 . A system comprising:
a compiler configured to:
identify a first set of neural network models that have been executed on a hardware accelerator of a computing device more than a threshold number of times in a preset amount of time in the past;
identify a sequence in which the first set of models are executed on the hardware accelerator;
compile each neural network model of the first set of neural network models in the sequence for execution by the hardware accelerator and assigning a first hash to the identified sequence of models;
output, for each neural network model of the first set of neural network models in the sequence, the compiled model to the hardware accelerator for storage in one or more memories of the hardware accelerator;
compiling a second sequence of neural network models and computing a second hash for the second sequence of neural network models;
determining that the first hash matches the second hash; and
in response, bypassing loading compiled models in the second sequence of neural network models into storage of the hardware accelerator;
the hardware accelerator comprising the one or more memories to store the compiled model for each neural network model of the first set of neural network models according to the sequence, the storage according to the sequence of the compiled model for each neural network model of the first set of neural network models in the one or more memories preventing a need for reloading a compiled result recompilation of the sequence of the first set of neural network models into the one or more memories when the first set of neural network models are to be executed again on the hardware accelerator.
13 . The system of claim 12 , wherein the one or more memories is static random access memory (SRAM).
14 . The system of claim 12 , wherein the hardware accelerator further comprises a plurality of computing units, each comprising at least one processor, configured to process the first set of neural network models.
15 . The system of claim 14 , wherein:
each computing unit of the plurality of computing units further comprises a memory; and
the plurality of computing units are coupled serially via at least one bus.
16 . The system of claim 12 , wherein the first set of neural network models include at least one face recognition neural network model.
17 . The system of claim 16 , wherein the at least one face recognition neural network model is activated in response to the controller receiving an instruction from the computing device to execute the at least one face recognition neural network model.
18 . The system of claim 17 , wherein the computing device comprises an application and an application programming interface (API), the application generating the instruction to be sent via the API.
19 . The system of claim 18 , wherein the application is a camera application.
20 . The system of claim 18 , wherein:
the API is a Neural Networks API (NNAPI); and
the computing device is an Android device.