IP Library › Granted Patent US 12,585,920
Granted Patent B2
US 12,585,920 · App. 18/309,438 · Granted Mar 24, 2026

Predicting optimal parameters for physical design synthesis

Inventors: Michael Kazda (Poughkeepsie, NY); Michael Daniel Monkowski (New Windsor, NY)
Assignee: International Business Machines Corporation
G06N3/0455G06F30/327G06N3/0895
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Quick Facts
Patent No.
US 12,585,920
App. No.
18/309,438
Filed
Apr 28, 2023
Granted
Mar 24, 2026
Kind
B2
Art Unit
2124
USPC
706/21
Abstract

Embodiments of the present disclosure provide enhanced systems and methods for predicting optimal design flow parameters for optimized output targets for physical design synthesis of a given IC design. A Variational Autoencoder (VAE) along with a regression network are trained using a dataset comprising synthesis design construction flows from historical IC designs to provide a training data representation of the dataset constrained to a latent space of the VAE. The system generates feature vectors based on the training data representation of the dataset and updates the feature vectors with initial design characteristics of the given IC design. The system iteratively performs an input gradient search of the updated feature vectors to optimize an objective function of the design targets to identify locally optimal design parameters. The system identifies globally optimal design flow parameters for optimized design targets based on locally optimal design parameters.

Claims (42)

1 . A method comprising:

receiving initial design characteristics, design flow parameters, and design targets from a design construction flow for a given integrated circuit (IC) design;

receiving a historical dataset comprising synthesis design construction flows from historical IC designs;

training a Variational Autoencoder (VAE) along with a regression network using the historical dataset to provide a training data representation of the dataset constrained to a latent space of the VAE;

generating feature vectors based on the training data representation of the dataset and updating the feature vectors with the initial design characteristics;

iteratively performing an input gradient search of the updated feature vectors to optimize an objective function of the design targets to identify locally optimal design parameters, wherein the training data samples are constrained to the initial design characteristics; and

obtaining a prediction of global optimal design flow parameters based on the identified locally optimal design parameters for optimized design targets.

2 . The method of claim 1 , further comprises decoding a random set of samples from the training data representation of the dataset to generate feature vectors comprising design characteristics and design flow parameters; and wherein updating the feature vectors with the initial design characteristics comprises replacing design characteristics in the generated feature vectors with the initial design characteristics to provide the updated feature vectors.

3 . The method of claim 1 , wherein iteratively performing the input gradient search further comprises calculating an input gradient for each optimization epoch, applying the input gradient to modify next design flow parameters for a next optimization iteration.

4 . The method of claim 1 , wherein obtaining the prediction of global optimal design flow parameters based on the locally optimal design parameters for the optimized design targets further comprises performing quantization of at least one binary parameter element of the global optimal design flow parameters.

5 . The method of claim 1 , further comprises building the VAE comprising an encoder, the latent space, and a decoder; and wherein the encoder comprises one or more neural network layers with a first plurality nodes on an inner layer and a second plurality of nodes on outer layer; wherein the decoder comprises one or more neural network layers with the second plurality of nodes on a decoder inner layer and the first plurality nodes on a decoder outer layer and wherein the latent space comprises a random sample layer comprising multiple nodes.

6 . The method of claim 1 , wherein obtaining the prediction of global optimal design flow parameters based on the identified locally optimal design parameters for the optimized design targets further comprises sorting the locally optimal design parameters based on the objective function to identify the global optimal design flow parameters.

7 . The method of claim 1 , wherein training the VAE along with the regression network further comprises performing interpolation training of the VAE along with the regression network using combined interpolated vectors and training vectors to minimize a reconstruction error of the training data representation of the dataset.

8 . The method of claim 1 , wherein training the VAE along with the regression network further comprises performing training of the VAE along with the regression network using unsupervised machine learning with a vector of training data features and supervised machine learning with a vector of training data output targets to provide the training data representation of the dataset constrained to the latent space of the VAE.

9 . The method of claim 1 , wherein training the VAE along with the regression network further comprises generating interpolated vectors of the dataset, and combining the interpolated vectors with training vectors to produce an augmented dataset each epoch.

10 . The method of claim 1 , wherein iteratively performing the input gradient search further comprises using hyperparameter values comprising at least one of a regression weight, a reconstruction weight, a number of epochs for training or a training batch size.

11 . The method of claim 1 , wherein the regression network is connected to a neural network layer of the VAE that represents the latent space.

12 . A system, comprising:

a processor; and

a memory, wherein the memory includes a computer program product configured to perform operations for predicting optimal design flow parameters for physical design synthesis of a given integrated circuit (IC) design, the operations comprising:

receiving initial design characteristics, design flow parameters, and design targets from a design construction flow for the given integrated circuit (IC) design;

receiving a historical dataset comprising synthesis design construction flows from historical IC designs;

training a Variational Autoencoder (VAE) along with a regression network using the historical dataset to provide a training data representation of the dataset constrained to a latent space of the VAE;

generating feature vectors based on the training data representation of the dataset and updating the feature vectors with the initial design characteristics;

iteratively performing an input gradient search of the updated feature vectors to optimize an objective function of the design targets to identify locally optimal design parameters, wherein the training data samples are constrained to the initial design characteristics; and

obtaining a prediction of global optimal design flow parameters based on the identified locally optimal design parameters for optimized design targets.

13 . The system of claim 12 , further comprises decoding a random set of samples from the training data representation of the dataset to generate feature vectors comprising design characteristics and design flow parameters; and wherein updating the feature vectors with the initial design characteristics comprises replacing design characteristics in the generated feature vectors with the initial design characteristics to provide the updated feature vectors.

14 . The system of claim 12 , wherein training the VAE along with the regression network further comprises performing training of the VAE along with the regression network using unsupervised machine learning with a vector of training data features and supervised machine learning with a vector of training data output targets to provide the training data representation of the dataset constrained to the latent space of the VAE.

15 . The system of claim 12 , wherein iteratively performing the input gradient search further comprises calculating an input gradient for each optimization epoch, applying the input gradient to modify next design flow parameters for a next optimization epoch.

16 . The system of claim 12 , wherein obtaining the prediction of global optimal design flow parameters further comprises performing quantization of at least one binary parameter element of global optimal design flow parameters.

17 . A computer program product for implementing prediction of optimal design flow parameters for physical design synthesis of a given integrated circuit (IC) design, the computer program product comprising:

a computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code executable by one or more computer processors to perform an operation comprising:

receiving initial design characteristics, design flow parameters, and design targets from a design construction flow for a given integrated circuit (IC) design;

receiving a historical dataset comprising synthesis design construction flows from historical IC designs;

training a Variational Autoencoder (VAE) along with a regression network using the historical dataset to provide a training data representation of the dataset constrained to a latent space of the VAE;

generating feature vectors based on the training data representation of the dataset and updating the feature vectors with the initial design characteristics;

iteratively performing an input gradient search of the updated feature vectors to optimize an objective function of the design targets to identify locally optimal design parameters, wherein the training data samples are constrained to the initial design characteristics; and

obtaining a prediction of global optimal design flow parameters based on the identified locally optimal design parameters for optimized design targets.

18 . The computer program product of claim 17 , further comprises sorting the locally optimal design parameters based the objective function to obtain the prediction of globally optimal design flow parameters for the given IC design.

19 . The computer program product of claim 17 , wherein training the VAE along with the regression network further comprises generating interpolated vectors of the dataset, and combining the interpolated vectors with training vectors to produce an augmented dataset each epoch.

20 . The computer program product of claim 17 , wherein training the VAE along with the regression network further comprises performing training of the VAE along with the regression network using unsupervised machine learning with a vector of training data features and supervised machine learning with a vector of training data output targets to provide the training data representation of the dataset constrained to the latent space of the VAE.

21 . The computer program product of claim 16 , further comprises decoding a random set of samples from the training data representation of the dataset to generate the feature vectors comprising design characteristics and design flow parameters; and wherein updating the feature vectors with the initial design characteristics comprises replacing design characteristics in the generated feature vectors with the initial design characteristics to provide the updated feature vectors.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 28, 2023
From: KAZDA, MICHAEL; MONKOWSKI, MICHAEL DANIEL
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 063482/0766 →
Continuity (1)
Related Publication 20240362459A1 · Oct 31, 2024
References Cited (55)
US 7337420B2 · Chidambarrao et al. · 2008 [cited by applicant]
US 11354582B1 · Prat et al. · 2022 [cited by applicant]
US 11373096B2 · Chidlovskii et al. · 2022 [cited by applicant]
US 11568961B2 · Bucher et al. · 2023 [cited by applicant]
US 20190370435A1 · Sha et al. · 2019 [cited by applicant]
US 20220138388A1 · Wang et al. · 2022 [cited by applicant]
US 20220335286A1 · Cummings et al. · 2022 [cited by applicant]
US 20250077888A1 · Monkowski et al. · 2025 [cited by applicant]
WO 20200112023A1 · 2020 [cited by applicant]
WO 20200197529A1 · 2020 [cited by applicant]
WO 2020251680A1 · 2020 [cited by applicant]
WO 2021170735A1 · 2021 [cited by applicant]
WO 2022144203A1 · 2022 [cited by applicant]
WO 2024223404A1 · 2024 [cited by applicant]
Zhu, Keren, Mingjie Liu, Yibo Lin, Biying Xu, Shaolan Li, Xiyuan Tang, Nan Sun, and David Z. Pan. “Genius Route: A new analog routing paradigm using generative neural network guidance.” In 2019 IEEE/ACM International Co… [cited by examiner]
Ning F, Ma Y, Yang H, Yu B, Yang H, Wang Y. Machine Learning for Electronic Design Automation: A Survey. arXiv preprint arXiv: 2102.03357. Feb. 2021. (Year: 2021). [cited by examiner]
International Search Report and Written Opinion for International Application No. PCT/EP2024/060563 Mailed Aug. 28, 2024. [cited by applicant]
Habal, et al.: “Constraint-Based Layout-Driven Sizing of Analog Circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, USA, vol. 30, No. 8, Aug. 1, 2011 (Aug. 1, 2011) | pp. 1089… [cited by applicant]
Fchollet, “Keras documentation: Variational AutoEncoder”, Keras Teasm, URL: https://keras.io/examples/generative/vae/, Date Created: May 3, 2020, Last Modified: May 3, 2020, Printed: May 8, 2023, 6 pages. [cited by applicant]
Garciarena et al., “Expanding variational autoencoders for learning and exploiting latent representations in search distributions”, ACM, GECCO '18: Proceedings of the Genetic and Evolutionary Computation Conference, htt… [cited by applicant]
Huang et al., “A Dimension-Reduced Artificial Neural Network for the Compact Modeling of Semiconductor Devices”, Conference: 2018 IEEE MTT-S International Wireless Symposium (IWS), DOI:10.1109/IEEE-IWS.2018.8400840, dat… [cited by applicant]
Kazda et al., “Recommending Design Flow Parameters Using a Variational Autoencoder”, URL: https://arxiv.org/pdf/1802.05814, 2022, Woodstock '18: ACM Symposium on Neural Gaze Detection, Jun. 3-5, 2018, Woodstock, NY. AC,… [cited by applicant]
Keren Zhu, “Fully-Automated Layout Synthesis for Analog and Mixed-Signal Integrated Circuits”, Dissertation, Electrical and Computer Engineering, The University of Texas at Austin, dated Aug. 2022, 70 pages. [cited by applicant]
Lee et al., “Layout-induced stress effects on the performance and variation of FinFETs”, 2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), DOI: 10.1109/SISPAD.2015.7292336, Dat… [cited by applicant]
Lin et al., “High Performance 14nm SOI FinFET CMOS Technology with 0.0174 μm2 embedded DRAM and 15 Levels of Cu Metallization”, 2014 IEEE International Electron Devices Meeting, DOI: 10.1109/IEDM.2014.7046977, Date Adde… [cited by applicant]
Mun et al., “14nm FinFET Technology SRAM Cell Margin Evaluation and Analysis by Local Layout Effect”, Conference: 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), DOI:10.1109/S3S.2017.… [cited by applicant]
Samsung, “Samsung Exynos Processor”, Samsung Semiconductor Global, URL: https://semiconductor.samsung.com/processor/, 2023, printed: May 8, 2023, 6 pages. [cited by applicant]
Samsung, FinFET Process, “Radical Innovation to Push the Limit for Greater Speed and Efficiency”, Samsung Exynos, URL: http://etest.ninefive.org/index.html, 2017, printed Mar. 29, 2023, 4 pages. [cited by applicant]
Sourodeep Bhattacharjee, “Variational Autoencoder Based Estimation Of Distribution Algorithms And Applications To Individual Based Ecosystem Modeling Using EcoSim”, University of Windsor, Electronic Theses and Dissertat… [cited by applicant]
Touloupas et al., “Mixed-Variable Bayesian Optimization for Analog Circuit Sizing using Veriational Autoencoders”, 2022 18th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applicati… [cited by applicant]
Tsutsui et al., “SiGe FinFET for Practical Logic Libraries by Mitigating Local Layout Effect”, 2017 Symposium on VLSI Technology Digest of Technical Papers, DOI: 10.23919/VLSIT.2017.7998215, Date Added to IEEE Xplore: A… [cited by applicant]
Van Cleef et al., “BonnCell: Automatic Cell Layout in the 7-nm era”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, No. 10, dated Oct. 2020, 14 pages. [cited by applicant]
Wen et al., “Fin Bending Mitigation and Local Layout Effect Alleviation in Advanced FinFET Technology through Material Engineering and Metrology Optimization”, 2019 Symposium on VLSI Technology, DOI: 10.23919/VLSIT.2019… [cited by applicant]
Yang et al., “10nm High Performance Mobile SoC Design and Technology Co-Developed for Performance, Power, and Area Scaling”, 2017 Symposium on VLSI Technology Digest of Technical Papers, DOI: 10.23919/VLSIT.2017.7998203… [cited by applicant]
Zhang et al., “Local Layout Effect Impact to Single Device in Sram 6T Cell,” 2019 China Semiconductor Technology International Conference (CSTIC), DOI: 10.1109/CSTIC.2019.8755621, Date Added to IEEE Xplore: Jul. 8, 2019… [cited by applicant]
Zhao et al., “Influence of stress induced CT local layout effect (LLE) on 14nm FinFET”, 2017 Symposium on VLSI Technology Digest of Technical Papers, DOI:10.23919/VLSIT.2017.7998182, Published Jun. 1, 2017, 2 pages. [cited by applicant]
Zwerdling et al., “Understanding the Properties if Generated Corpora”, IBM Research, arXivL2206.11219v2 [cs.CL], https://doi.org/10.48550/arXiv.2206.11219, dated Oct. 27, 2022, 7 pages. [cited by applicant]
Agnesina, Anthony, Kyungwook Chang, and Sung Kyu Lim. “VLSI placement parameter optimization using deep reinforcement learning.” Proceedings of the 39th International Conference on Computer-Aided Design. 2020. pp. 1-9. [cited by applicant]
Clement Chadebec et al., “Data Augmentation in High Dimensional Low Sample Size Setting Using a Geometry-Based Variational Autoencoder,” arXiv, Dated: Apr. 30, 2021, pp. 1-25. [cited by applicant]
F. Chollet, “Variational AutoEncoder,” Keras, Dated: May 3, 2020, pp. 1-6. [cited by applicant]
Geng, Hao, et al. “Techniques for CAD tool parameter auto-tuning in physical synthesis: a survey.” 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 2022. pp. 1-6. [cited by applicant]
Huang, Wenbing, et al. “Scalable Gaussian process regression using deep neural networks.” Twenty-fourth international joint conference on artificial intelligence. 2015. pp. 1-7. [cited by applicant]
D. Kingma et al., “Auto-Encoding Variational Bayes,” arXiv.org, Dated: May 1, 2014, pp. 1-14. [cited by applicant]
Kingma, Durk P., et al. “Semi-supervised learning with deep generative models.” Advances in neural information processing systems 27 (2014). pp. 1-9. [cited by applicant]
Kwon, Jihye, Matthew M. Ziegler, and Luca P. Carloni. “A learning-based recommender system for autotuning design flows of industrial high-performance processors.” Proceedings of the 56th Annual Design Automation Confere… [cited by applicant]
Alon Oring et al., “Autoencoder Image Interpolation by Shaping the Latent Space,” arXiv.org, Dated: Oct. 22, 2020, pp. 1-21. [cited by applicant]
S. Khan et al., “Adversarial Training of Variational Auto-encoders for High Fidelity Image Generation,” arXiv.org, Dated: Apr. 27, 2018, pp. 1-9. [cited by applicant]
Safir, Nathan Samuel. Variational Autoencoders For Semi-Supervised Deep Metric Learning. Diss. University of Georgia, 2022. pp. 1-9. [cited by applicant]
Steven Flores, “Variational Autoencoders are Beautiful,” Blogs, Dated: Apr. 15, 2019, pp. 1-10. [cited by applicant]
Y. Takida et al., “Preventing Posterior Collapse Induced by Oversmoothing in Gaussian VAE,” arXiv.org, Dated: Feb. 17, 2021, pp. 1-21. [cited by applicant]
Z. Xie et al., “Fist: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning,” arXiv.org, Dated: Nov. 26, 2020, pp. 1-7. [cited by applicant]
Yoo, YoungJoon, et al. “Variational autoencoded regression: high dimensional regression of visual data on complex manifold.” Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition. 2017. pp. 1-10. [cited by applicant]
Shen Zhang et al., “Semi-Supervised Learning of Bearing Anomaly Detection via Deep Variational Autoencoders,” arXiv.org, Dated: Dec. 9, 2019, pp. 1-11. [cited by applicant]
Qingyu Zhao et al., “Variational AutoEncoder for Regression: Application to Brain Aging Analysis,” arXiv.org, Dated: Jul. 11, 2019, pp. 1-9. [cited by applicant]
Ziegler, Matthew M., Hung-Yi Liu, and Luca P. Carloni. “Scalable auto-tuning of synthesis parameters for optimizing high-performance processors.” Proceedings of the 2016 International Symposium on Low Power Electronics … [cited by applicant]