Integrated memory system for high performance Bayesian and classical inference of neural networks
A memory module system for a high-dimensional weight space neural network configured to process machine learning data streams using Bayesian Inference and/or Classical Inference is set forth. The memory module can include embedded high speed random number generators (RNGs). The memory module is configured to compute, store and sample neural network weights by adapting operating precision to optimize the computing effort based on available weight space and application specifications.
1 . A memory module system for a high-dimensional weight space neural network configured to process machine learning data streams comprising:
a memory module comprising a static random access memory (SRAM) array and a cross-SRAM processing layer, the SRAM array comprising an array of SRAM cells, multiplexer, analog-to-digital converter (ADC) and multiplicand buffer, the memory module with embedded random number generators (RNGs) within the memory module, where the SRAM array is configured for scalar product computation to determine statistical density storage;
the memory module configured to store neural network weights, sample the neural network weights, and compute one or more scalar product using the sampled neural network weights and one or more corresponding applied inputs, where the memory module adapts operating precision to optimize computing effort based on available weight space and application specifications; and
transform the one or more scalar product into an output signal.
2 . The memory module system of claim 1 , further comprising at least one scalar product port.
3 . The memory module system of claim 1 , wherein the memory module is incorporated in an edge processing device.
4 . The memory module system of claim 1 , further comprising at least one peripheral digital to analog converter (DAC) operatively connected to the multiplicand buffer and to a row current of the SRAM array, wherein the row current provides a current-mode AND gate for the DAC.
5 . The memory module system of claim 4 , wherein Gaussian mixture model (GMM) density computations are mapped onto the SRAM array.
6 . The memory model system of claim 3 , wherein Gaussian mixture module (GMM) density computations are mapped onto an integrated memory array (IMA) of the edge processing device.