IP Library › Granted Patent US 12,587,610
Granted Patent B2
US 12,587,610 · App. 19/001,841 · Granted Mar 24, 2026

Circuit apparatus and display system

Inventor: Yasutoshi Akiba (Chino, JP)
Assignee: SEIKO EPSON CORPORATION
H04N7/0881H04N5/06H04N7/0127
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Quick Facts
Patent No.
US 12,587,610
App. No.
19/001,841
Granted
Mar 24, 2026
Kind
B2
Abstract

A first selection circuit switches from first image data to switching image data in a vertical blanking period of the first image data. An output circuit outputs output image data at a frame rate different from that of second image data in a switching period in which the switching image data is selected by the first selection circuit. The first selection circuit switches from the switching image data to the second image data in an overlap period between a vertical blanking period of the switching image data and a vertical blanking period of the second image data.

Claims (37)

1 . A circuit apparatus comprising:

a first input circuit configured to receive first image data;

a second input circuit configured to receive second image data;

a frame memory configured to store the second image data as switching image data;

a first selection circuit configured to select any of the first image data, the second image data, and the switching image data and output the selected image data as first selected image data;

an output circuit configured to output image data based on the first selected image data; and

a control circuit, wherein

the control circuit

controls the first selection circuit to switch from the first image data to the switching image data in a vertical blanking period of the first image data,

controls the output circuit to output the output image data at a frame rate different from a frame rate of the second image data in a switching period in which the switching image data is selected by the first selection circuit, and

controls the first selection circuit to switch from the switching image data to the second image data in an overlap period between a vertical blanking period of the switching image data and a vertical blanking period of the second image data.

2 . The circuit apparatus according to claim 1 , further comprising:

a compression circuit configured to compress the second image data, wherein

the frame memory stores, as the switching image data, the second image data compressed by the compression circuit.

3 . The circuit apparatus according to claim 2 , further comprising:

a decompression circuit configured to decompress the switching image data stored in the frame memory and output the decompressed switching image data to the first selection circuit.

4 . The circuit apparatus according to claim 1 , wherein

the control circuit sets a frame rate of the switching image data to a frame rate lower than the frame rate of the second image data.

5 . The circuit apparatus according to claim 1 , further comprising:

a second selection circuit configured to select any of the first image data and the second image data and output the selected image data as second selected image data, wherein

the frame memory stores the second selected image data as the switching image data.

6 . The circuit apparatus according to claim 5 , wherein

the second selection circuit selects the first image data as the second selected image data when the first selection circuit switches from the second image data to the first image data, and

the control circuit

controls the first selection circuit to switch from the second image data to the switching image data in the vertical blanking period of the second image data,

sets a frame rate of the switching image data to a frame rate different from a frame rate of the first image data in the switching period, and

controls the first selection circuit to switch from the switching image data to the first image data in an overlap period between the vertical blanking period of the switching image data and the vertical blanking period of the first image data.

7 . The circuit apparatus according to claim 1 , wherein

the control circuit sets a frame rate of the switching image data by adjusting a length of the vertical blanking period, a length of a horizontal blanking period, or the length of the vertical blanking period and the length of the horizontal blanking period of the switching image data in the switching period.

8 . The circuit apparatus according to claim 7 , further comprising:

a register configured to store adjustment data of the frame rate of the switching image data, wherein

the control circuit sets the length of the vertical blanking period, the length of the horizontal blanking period, or the lengths of the vertical blanking period and the horizontal blanking period of the switching image data based on the adjustment data in the switching period.

9 . The circuit apparatus according to claim 1 , wherein

when the first selection circuit selects any of the first image data, the switching image data, and the second image data, the output circuit outputs the output image data based on a dot clock signal of the same frequency.

10 . A display system comprising:

the circuit apparatus according to claim 1 ; and

a display apparatus configured to display an image based on the output image data.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 26, 2024
From: AKIBA, YASUTOSHI
To: SEIKO EPSON CORPORATION
Reel/Frame 069680/0693 →
Priority Claims (1)
JP 2023-220249 · Dec 27, 2023 · national
Continuity (1)
Related Publication 20250220135A1 · Jul 3, 2025
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