In-situ memory compression
The subject application relates to in-situ compression of data in a main memory and storing of the compressed data in the same main memory to improve memory optimization. A hardware logic of a memory device may receive modified pages from a first portion of memory array, cause a page compression accelerator in the hardware logic to compress the received modified pages to generate compressed data, and facilitate storing of the compressed data to a second portion of memory array of the same memory device. By using in-situ data compression, memory optimization in a computing device is improved.
1 . A memory module, comprising:
a volatile random access memory (RAM) array; and
complimentary metal oxide semiconductor (CMOS) logic under the RAM array on the memory module, the CMOS logic including a page compression accelerator (PCA) that is coupled to the volatile RAM array, wherein the CMOS logic is configured to:
receive data comprising pages marked as dirty pages from a first portion of the RAM array;
cause the PCA to compress the data to generate compressed data; and
cause the compressed data to be stored in a second portion of the volatile RAM array; and
wherein the memory module is configured to operate as main memory for a computing system.
2 . The memory module of claim 1 , wherein the CMOS logic is further configured to:
receive a command from a memory controller that is coupled to the CMOS logic, the command includes compressing the data using a compression ratio; and
in response to the received command, the CMOS logic is configured to:
cause the PCA to compress the data using the compression ratio; and
store the compression ratio associated with the stored compressed data.
3 . The memory module of claim 2 , wherein the CMOS logic is configured to:
receive a command from the memory controller, the command includes moving the stored compressed data from the second portion of the volatile RAM array to the first portion of the volatile RAM array; and
in response to the received command, the CMOS logic is configured to:
identify the compression ratio that is associated with the stored compressed data to be decompressed;
cause the PCA to use the identified compression ratio as a reference for decompressing the stored compression data to generate a decompressed data; and
store the decompressed data to the first portion of the volatile RAM array.
4 . The memory module of claim 1 , wherein the dirty pages include modified pages in the first portion of the volatile RAM array.
5 . The memory module of claim 1 , wherein the CMOS logic is configured to: cause the PCA to compress the modified pages; and
cause the compressed modified pages to be stored in the second portion of the volatile RAM array.
6 . The memory module of claim 1 , wherein the second portion of the volatile RAM array includes a compressed cache (zRAM) that is a partition of the volatile RAM array.
7 . The memory module of claim 1 , wherein the second portion of the volatile RAM array includes compressed block storage configured to store the compressed data.
8 . A memory module, comprising:
a first volatile random access memory (RAM) array;
a second volatile RAM array;
complimentary metal oxide semiconductor (CMOS) logic under the second volatile RAM array on the memory module, the CMOS logic including a page compression accelerator (PCA) that is coupled to the second volatile RAM array; and
a memory controller coupled to the first volatile RAM array and to the second volatile RAM array, wherein the memory controller is configured to move data comprising pages marked as dirty pages from the first volatile RAM array to the second volatile RAM array in response to a memory reclamation command,
wherein the CMOS logic is configured to:
cause the PCA to compress the data to generate compressed data; and
cause the compressed data to be stored in the second volatile RAM array; and
wherein the memory module is configured to operate as main memory for a computing system.
9 . The apparatus of claim 8 , wherein the CMOS logic is further configured to:
receive a command from the memory controller, the command includes compressing the data using a compression ratio; and
in response to the received command, the CMOS logic is configured to:
cause the PCA to compress the data using the compression ratio; and
store the compression ratio associated with the stored compressed data.
10 . The apparatus of claim 9 , wherein the CMOS logic is configured to:
receive a command from the memory controller, the command includes moving the stored compressed data from the second memory array to the first memory array; and
in response to the received command, the CMOS logic is configured to:
identify the compression ratio that is associated with the stored compressed data to be decompressed;
cause the PCA to use the identified compression ratio as a reference for decompressing the stored compression data to generate a decompressed data; and
send the decompressed data to the memory controller.
11 . The apparatus of claim 10 , wherein memory controller is configured to store the decompressed data in the first volatile RAM array.
12 . The apparatus of claim 8 , wherein the memory controller is configured to send an interrupt to a host to indicate the storing of the compressed data.
13 . A method, comprising:
receiving, by a complimentary metal oxide semiconductor (CMOS) logic under a volatile random access memory (RAM) array on a memory module, data comprising pages marked as dirty pages from a first portion of the volatile RAM array, wherein the CMOS logic is coupled to the volatile RAM array and includes a page compression accelerator (PCA);
receiving a command at the CMOS logic;
executing the command on the PCA to compress the received data to generate a compressed data;
storing the compressed data to a second portion of the volatile RAM array; and
operating the memory module as main memory for a computing system.
14 . The method of claim 13 , further comprising erasing the data in the first portion of the volatile RAM array in response to the storing of the compressed data in the second portion of the volatile RAM array.
15 . The method of claim 13 , further comprising:
receiving a command from a memory controller that is coupled to the CMOS logic, wherein the command includes moving the stored compressed data from the second portion of the volatile RAM array to the first portion of the volatile RAM array;
executing the command on the PCA to decompress the stored compressed data to generate a decompressed data; and
sending the decompressed data to the memory controller.
16 . The method of claim 13 , wherein the data includes dirty data.