Data processing method for processing unit, electronic device and computer readable storage medium
Embodiments of the present disclosure relate to a method for data processing and to the field of computers. The method comprises: in the m th clock cycle, determining a first exponent value; in the m+1 th clock cycle, inputting two n-dimensional vectors into the processing unit to determine n second exponent values; determining a maximum value among the first exponent value and the determined n second exponent values; determining whether a target second exponent value exists among the n second exponent values, an absolute value of a difference between the target second exponent value and the maximum value being greater than or equal to a first threshold; and in response to determining that the target second exponent value exists in n second exponent values, not performing a multiply operation of two floating point numbers corresponding to the target second exponent value in the processing unit, during the m+1 th clock cycle.
1 . A data processing method for systolic array, wherein the systolic array is an implementation of a general matrix multiply arithmetic logic unit and comprises a plurality of data processing units, each of the data processing units comprises a first source register, a second source register, a destination register and a calculation unit including a multiplier and an adder, a processor is used to control each of the data processing units for performing following steps, comprising:
in m th clock cycle, activating a timer to send a first clock control signal to the first source register and the second source register, so that in the m th clock cycle, the first source register inputs a first n-dimensional vector into the calculation unit which is a hardware logic component, and the second source register inputs a second n-dimensional vector into the calculation unit, performing a first dot product operation on the first n-dimensional vector and the second n-dimensional vector by the calculation unit, and determining a first exponent value of a floating point number of a result of the first dot product operation performed, and storing the first exponent value, where m is a positive integer greater than or equal to 1;
in m+1 th clock cycle, activating the timer to send a second clock control signal to the first source register and the second source register, so that in the m+1 th clock cycle, the first source register inputs a third n-dimensional vector into the calculation unit, and the second source register inputs fourth n-dimensional vector into the calculation unit, determining n second exponent values in the calculation unit, the second exponent values being obtained by adding the exponent of a floating point number in one of the third n-dimensional vector and the fourth n-dimensional vector with the exponent of a corresponding floating point number in the other of the two n-dimensional vectors, n being a positive integer greater than or equal to 1;
determining a maximum value among the first exponent value and the determined n second exponent values;
using a number of reserved bits of a mantissa of the floating point number stored in the destination register as a first threshold;
determining whether a target second exponent value exists among the n second exponent values, an absolute value of a difference between the target second exponent value and the maximum value being greater than or equal to the first threshold; and
in response to determining that the target second exponent value exists in n second exponent values, sending a signal to the multiplier of the calculation unit to cause the multiplier to bypass a multiply operation of two floating point numbers corresponding to the target second exponent value, during the m+1 th clock cycle.
2 . The data processing method according to claim 1 , wherein the processor is used to performing following steps, comprising: in response to determining that the target second exponent value does not exist among the n second exponent values, the multiply operation is performed for all data in the two n-dimensional vectors during the m+1 th clock cycle.
3 . The data processing method according to claim 1 , wherein the data processing unit comprises the destination register; and
an absolute value of a difference between the first threshold and the number of bits of the mantissa of the floating point number stored in the destination register is smaller than a second threshold.
4 . The data processing method according to claim 1 , wherein the first exponent value is obtained in the following manner:
in the m th clock cycle, performing the first dot product operation to obtain a floating point number of a first dot product operation result;
performing normalization processing for the floating point number of the first dot product operation result to obtain the first exponent value.
5 . The data processing method according to claim 4 , wherein performing the first dot product operation to obtain the floating point number of the first dot product operation result comprises:
multiplying i data from the first n-dimensional vector with corresponding i data from the second n-dimensional vector, respectively, to obtain i floating point numbers, where i=0, 1, 2 . . . n;
performing exponent matching processing on at least two floating point numbers among the i floating point numbers and the floating point numbers obtained by the dot product operation in m−1 th clock cycle;
summing the exponent matching processed floating point numbers, to obtain a floating point number of the first dot product operation result in the m th clock cycle.
6 . The data processing method according to claim 2 , wherein the exponent value of the floating point number of the result of the operation performed in the m+1 th clock cycle is determined as the first exponent value for comparison with the n second exponent values determined in m+2 th clock cycle.
7 . An electronic device, comprising:
a systolic array, comprising a plurality of data processing units, wherein each of the data processing units comprises a first source register, a second source register, destination register and a calculation unit including a multiplier and an adder, wherein the systolic array is an implementation of a general matrix multiply arithmetic logic unit;
a processor; and
a memory coupled to the processor, the memory having instructions stored therein, wherein the processor is configured to execute the instructions to control each of the data processing units to:
in m th clock cycle, activate a timer to send a first clock control signal to the first source register and the second source register, so that in the m th clock cycle, the first source register inputs a first n-dimensional vector into the calculation unit which is a hardware logic component, and the second source register inputs a second n-dimensional vector into the calculation unit, perform a first dot product operation on the first n-dimensional vector and the second n-dimensional vector by the calculation unit, and determine a first exponent value of a floating point number of a result of the first dot product operation performed, and store the first exponent value, where m is a positive integer greater than or equal to 1;
in m+1 th clock cycle, activate the timer to send a second clock control signal to the first source register and the second source register, so that in the m+1 th clock cycle, the first source register inputs a third n-dimensional vector into the calculation unit, and the second source register inputs a fourth n-dimensional vector into the calculation unit, determine n second exponent values in the calculation unit, and store the n second exponent values, the second exponent values being obtained by adding the exponent of a floating point number in one of the third n-dimensional vector and the fourth n-dimensional vector with the exponent of a corresponding floating point number in the other of the two n-dimensional vectors, n being a positive integer greater than or equal to 1;
determine a maximum value among the first exponent value and the determined n second exponent values;
use a number of reserved bits of a mantissa of the floating point number stored in a destination register as a first threshold;
determine whether a target second exponent value exists among the n second exponent values, an absolute value of a difference between the target second exponent value and the maximum value being greater than or equal to the first threshold; and
in response to determining that the target second exponent value exists in n second exponent values, send a signal to the multiplier of the calculation unit to cause the multiplier to bypass a multiply operation of two floating point numbers corresponding to the target second exponent value, during the m+1 th clock cycle.
8 . A non-transitory computer-readable storage medium having computer instructions stored thereon, the computer instructions, when executed by a machine, implementing the method according to claim 1 .