System and method for halting processing cores in a multicore system
A multicore computing device includes a memory and a processor coupled to the memory. The processor includes plural cores and a multiple input multiple output (MIMO) block coupled to the cores. The MIMO block receives a halt request from a first core of the cores, transmits a core-halt request to one or more other cores other than the first core, to halt execution of the one or more other cores, and permits the first core to lock with a shared resource.
1 . A multicore computing device comprising:
a memory; and
a processor coupled to the memory, the processor comprising:
a plurality of cores; and
a multiple input multiple output (MIMO) block coupled to the plurality of cores,
wherein the MIMO block comprises a timeout register and a HALT IP, the HALT IP being configured to:
receive a halt request from a first core of the plurality of cores;
transmit a core-halt request to one or more other cores of the plurality of cores other than the first core, to halt execution of the one or more other cores; and
permit the first core to continue execution and to lock with a shared resource,
wherein the halt request comprises a timeout duration and a list of the one or more other cores, and
wherein the MIMO block is configured to set the timeout register based on the timeout duration specified in the halt request.
2 . The multicore computing device as claimed in claim 1 , wherein the MIMO block is configured to transmit a resume instruction to each of the one or more other cores upon completion of a timeout for the timeout duration.
3 . The multicore computing device as claimed in claim 1 , wherein the MIMO block is configured to:
receive a release request from the first core, the release request indicating a release of the shared resource by the first core; and
transmit a resume instruction to each of the one or more other cores, based on the release request.
4 . The multicore computing device as claimed in claim 1 , wherein the MIMO block comprises an arbiter block.
5 . The multicore computing device as claimed in claim 4 , wherein the MIMO block is configured to receive the halt request from the first core and receive a halt request from a second core of the plurality of cores.
6 . The multicore computing device as claimed in claim 5 , wherein the arbiter block is configured to implement a first come first serve (FCFS) technique to select a service core from among the first core and the second core, and the service core that is selected services the halt request of the service core that is selected.
7 . The multicore computing device as claimed in claim 5 , wherein the arbiter block is configured to implement a round robin technique or a queue-based technique for servicing the halt requests from the first core and the second core.
8 . The multicore computing device as claimed in claim 1 , wherein the MIMO block is configured to:
check a current state of each of the one or more other cores;
identify a second core having an interrupt lock state, based on the current states; and
transmit a halt instruction to other cores except the second core that is identified.
9 . The multicore computing device as claimed in claim 1 , wherein the MIMO block is coupled to the plurality of cores using a bus, and
the bus comprises a BUS master.
10 . The multicore computing device as claimed in claim 9 , wherein at least two cores from the plurality of cores transmit a halt request to the MIMO block, and
wherein the BUS master is configured to:
identify that the halt requests are received from the at least two cores;
handle the halt requests based on one of: a First Come First Serve (FCFS) technique, a Round Robin (RR) technique, or a queue-based technique.
11 . The multicore computing device as claimed in claim 1 , further comprising a core manager configured to increase a frequency of the first core, based on the permission to lock with the shared resource.
12 . The multicore computing device as claimed in claim 1 , wherein the MIMO block comprises a purpose register configured to notify at least one system parameter change from at least one core of the plurality of cores to other cores of the plurality of cores other than the at least one core.
13 . The multicore computing device as claimed in claim 1 , wherein the MIMO block is coupled to the plurality of cores using a bus, and
the MIMO block is interfaced as a BUS master to a debug architecture.
14 . The multicore computing device as claimed in claim 1 , wherein the processor further comprises an event register coupled to the plurality of cores, and
the event register is configurable by each of the plurality of cores to perform a halt operation and a resume operation for other cores of the plurality of cores.
15 . A method comprising:
in a multicore computing device that includes a memory and a processor coupled to the memory, the processor including a plurality of cores and a multiple input multiple output (MIMO) block that is coupled to the plurality of cores and that comprises a timeout register:
receiving, by a HALT IP of the MIMO block, a halt request from a first core of the plurality of cores;
transmitting, by the HALT IP of the MIMO block, a core-halt request to one or more other cores of the plurality of cores other than the first core, to halt execution of the one or more other cores; and
permitting, by the HALT IP of the MIMO block, the first core continue execution and to lock with a shared resource,
wherein the halt request comprises a timeout duration and a list of the one or more other cores and
wherein the MIMO block is configured to set the timeout register based on the timeout duration specified in the halt request.
16 . The method as claimed in claim 15 , further comprising: transmitting, by the MIMO block, a resume instruction to each of the one or more other cores upon completion of a timeout for the timeout duration.