Off-state isolation bias circuit for D-mode amplifiers
A circuit comprises an amplifier and a bias circuit. The amplifier comprises an output transistor comprising a source electrode, a drain electrode, and a gate electrode. The bias circuit comprises: a first control loop configured to set a first quiescent bias for the output transistor based on a first value of a first control voltage and a second value of a second control voltage, wherein the first quiescent bias is configured to put the output transistor in an on state; and a second control loop configured to set a second quiescent bias for the output transistor based on the first value of the first control voltage and the second value of the second control voltage. The second quiescent bias is configured to put the output transistor in an off state and to increase an insertion loss of the amplifier when the output transistor is in the off state.
1 . A circuit, comprising:
a first amplifier comprising a first output transistor, the first output transistor comprising a first source electrode, a first drain electrode, and a first gate electrode; and
a bias circuit in operable communication with the first amplifier, the bias circuit comprising:
a first control loop configured to set a first quiescent bias for the first output transistor based on a first value of a first control voltage and a second value of a second control voltage, wherein the first quiescent bias is configured to put the first output transistor in an “on” state;
a second control loop configured to set a second quiescent bias for the first output transistor based on the first value of the first control voltage and the second value of the second control voltage, wherein the second quiescent bias is configured to put the first output transistor in an “off” state and to increase an insertion loss of the first amplifier when the first output transistor is in the “off” state; and
a first level shifting network having a first terminal coupled to a node common to the first control loop and the second control loop and a second control terminal coupled to the first gate electrode, the first level shifting network being shared by the first control loop and the second control loop and configured to level shift a signal provided to the first gate electrode.
2 . The circuit of claim 1 , wherein the bias circuit is configured to provide a first output signal to the first gate electrode, the first output signal based on at least one of the first control loop and the second control loop.
3 . The circuit of claim 2 , wherein at least one of the first control loop and the second control loop further comprises a second level shifting network configured to provide a second level shifting in a level of the first output signal.
4 . The circuit of claim 3 , wherein the second level shifting network comprises at least one of a diode, a resistor, and a short circuit connection.
5 . The circuit of claim 1 , wherein:
the first control loop and the second control loop are each coupled to a node that is coupled to a first end of the first level shifting network; and
a second end of the first level shifting network is coupled to the first gate electrode of the first amplifier.
6 . The circuit of claim 1 , wherein the first level shifting network comprises at least one of a diode, a resistor, and a short circuit connection.
7 . The circuit of claim 1 , wherein the second quiescent bias is configured to:
set a voltage at the first gate electrode to a value that is positive relative to a pinch-off voltage of the first output transistor; and
form a resistance between the first drain electrode and the first source electrode that is low enough to enable conduction to ground between the first drain electrode and the first source electrode.
8 . The circuit of claim 1 , wherein one of the first and second control voltages is coupled to the first drain electrode of the first amplifier.
9 . The circuit of claim 1 , wherein, if the first control voltage is at a logic high level and the second control voltage is at a logic low level, the first control loop is configured to set the first quiescent bias to put the first output transistor in the “on” state.
10 . The circuit of claim 1 , wherein, if the first control voltage is at a logic low level and the second control voltage is at a logic high level, the second control loop is configured to set the second quiescent bias to put the first output transistor in the “off” state.
11 . The circuit of claim 1 , wherein at least one of the first control loop and the second control loop further comprises a diode network comprising at least one diode, wherein the diode network is configured to isolate at least a portion of the first control loop from the second control loop.
12 . The circuit of claim 1 , further comprising a second amplifier comprising a second output transistor, the second output transistor comprising a second source electrode, a second drain electrode, and a second gate electrode, wherein:
the bias circuit is in operable communication with the second amplifier;
the first control loop is configured to set a third quiescent bias for the second output transistor based on the first value of the first control voltage and the second value of the second control voltage, wherein the third quiescent bias is configured to put the second output transistor in an “off” state and to increase an insertion loss of the second amplifier when the second output transistor is in the “off” state; and
the second control loop is configured to set a fourth quiescent bias for the second output transistor based on the first value of the first control voltage and the second value of the second control voltage, wherein the fourth quiescent bias is configured to put the second output transistor in an “on” state.
13 . The circuit of claim 12 , wherein the first control loop and the second control loop are configured so that, if the first control voltage is at a logic high level and the second control voltage is at a logic low level, the first control loop sets the first quiescent bias to put the first output transistor in the “on” state and sets the third quiescent bias to put the second output transistor in the “off” state.
14 . The circuit of claim 12 , wherein the first control loop and the second control loop are configured so that, if the first control voltage is at a logic low level and the second control voltage is at a logic high level, the second control loop sets the first quiescent bias to put the first output transistor in the “off” state and sets the fourth quiescent bias to put the second output transistor in the “on” state.
15 . The circuit of claim 12 , wherein the bias circuit is configured to provide a second output signal to the second gate electrode, the second output signal based on at least one of the first control loop and the second control loop.
16 . The circuit of claim 1 , wherein the first output transistor is a depletion mode transistor.
17 . The circuit of claim 1 , wherein at least one of the first control loop and the second control loop comprises a plurality of control loops.
18 . The circuit of claim 1 , wherein at least one of the first control voltage and the second control voltage is associated with a range of voltage values.
19 . A method, comprising:
providing a first amplifier comprising a first output transistor, the first output transistor comprising a first source electrode, a first drain electrode, and a first gate electrode;
operably coupling a bias circuit to the first amplifier, the bias circuit comprising:
a first control loop configured to set a first quiescent bias for the first output transistor based on a first value of a first control voltage and a second value of a second control voltage, wherein the first quiescent bias is configured to put the first output transistor in an “on” state;
a second control loop configured to set a second quiescent bias for the first output transistor based on the first value of the first control voltage and the second value of the second control voltage, wherein the second quiescent bias is configured to put the first output transistor in an “off” state and to increase an insertion loss of the first amplifier when the first output transistor is in the “off” state; and
a level shifting network configured to be shared by the first control loop and the second control loop; and
providing a first output signal to the first gate electrode, the first output signal based on at least one of the first control loop and the second control loop and level shifted by the level shifting network.
20 . The method of claim 19 , further comprising:
setting a voltage at the first gate electrode to a value that is positive relative to a pinch-off voltage of the first output transistor; and
forming a resistance between the first drain electrode and the first source electrode that is low enough to enable conduction to ground between the first drain electrode and the first source electrode.