IP Library › Granted Patent US 12,592,690
Granted Patent B2
US 12,592,690 · App. 18/460,407 · Granted Mar 31, 2026

Control circuit

Inventors: Shinsuke Niino (Yokohama Kanagawa, JP); Masayuki Ozaki (Kawasaki Kanagawa, JP)
Assignees: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
H03K17/04123H03K17/6871H03K19/018514
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Quick Facts
Patent No.
US 12,592,690
App. No.
18/460,407
Granted
Mar 31, 2026
Kind
B2
Abstract

According to one embodiment, a control circuit includes a capacitive element connected between an output terminal of an output-switching transistor circuit and a control electrode, and a charge circuit charges the capacitive element when the ON/OFF switching signal is switched from an OFF command to an ON command, delay improvement circuit shortens a delay time from OFF to ON of the transistor circuit by setting the ON/OFF control voltage of the transistor circuit to the first switching threshold in conjunction with the operation of the charge circuit.

Claims (24)

1 . A control circuit comprising:

a transistor circuit which switches a voltage at an output terminal between a first voltage and a second voltage different from the first voltage according to an ON/OFF control voltage supplied to a control electrode;

a capacitive element connected between the output terminal of the transistor circuit and the control electrode;

a charge circuit which charges the capacitive element when an ON/OFF switching signal that generates the ON/OFF control voltage is switched from an OFF command to an ON command; and

a delay improvement circuit which sets the ON/OFF control voltage to a switching threshold in conjunction with operation of the charge circuit, thereby shortening a delay time of the transistor circuit which occurs when switched from an OFF state to an ON state.

2 . The control circuit of claim 1 , wherein

the delay improvement circuit comprises a switch element that turns ON and OFF in response to the ON/OFF switching signal, and a current adjustment circuit that adjusts a charge current to the capacitive element so that the ON/OFF control voltage is set to the switching threshold when the switch element is switched from an OFF state to an ON state by the ON/OFF switching signal.

3 . A control circuit comprising:

a transistor circuit which switches a voltage at an output terminal between a first voltage and a second voltage different from the first voltage according to an ON/OFF control voltage supplied to a control electrode;

a capacitive element connected between the output terminal of the transistor circuit and the control electrode;

a discharge circuit which discharges the capacitive element when an ON/OFF switching signal that generates the ON/OFF control voltage is switched from an ON command to an OFF command; and

a delay improvement circuit which sets the ON/OFF control voltage to a switching threshold in conjunction with operation of the discharge circuit, thereby shortening a delay time of the transistor circuit which occurs when switched from an ON state to an OFF state.

4 . The control circuit of claim 3 , wherein

the delay improvement circuit comprises a switch element that turns ON and OFF in response to the ON/OFF switching signal, and a current adjustment circuit that adjusts a discharge current to the capacitive element so that the ON/OFF control voltage is set to the switching threshold when the switch element is switched from an OFF state to an ON state by the ON/OFF switching signal.

5 . A control circuit comprising:

a transistor circuit which switches a voltage at an output terminal between a first voltage and a second voltage different from the first voltage according to an ON/OFF control voltage supplied to a control electrode;

a capacitive element connected between the output terminal of the transistor circuit and the control electrode;

a charge circuit which charges the capacitive element when an ON/OFF switching signal that generates the ON/OFF control voltage is switched from an OFF command to an ON command;

a discharge circuit which discharges the capacitive element when an ON/OFF switching signal that generates the ON/OFF control voltage is switched from an ON command to an OFF command;

a first delay improvement circuit which sets the ON/OFF control voltage to a switching threshold in conjunction with operation of the charge circuit, thereby shortening a delay time of the transistor circuit which occurs when switched from an OFF state to an ON state; and

a second delay improvement circuit which sets the ON/OFF control voltage to a switching threshold in conjunction with operation of the discharge circuit, thereby shortening a delay time of the transistor circuit which occurs when switched from the ON state to the OFF state.

6 . The control circuit of claim 5 , wherein

the first delay improvement circuit comprises a first switch element which turns ON and OFF in response to the ON/OFF switching signal, and a first current adjustment circuit which adjusts a charge current of the capacitive element so that the ON/OFF control voltage is set to the first switching threshold when the first switch element is switched from an OFF state to an ON state by the ON/OFF switching signal, and

the second delay improvement circuit comprises a second switch element which turns ON and OFF in response to the ON/OFF switching signal, and a second current adjustment circuit that adjusts a discharge current of the capacitive element so that the ON/OFF control voltage is set to the second switching threshold when the second switch element is switched from the ON state to the OFF state by the ON/OFF switching signal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 21, 2024
From: NIINO, SHINSUKE; OZAKI, MASAYUKI
To: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Reel/Frame 066514/0209 →
Priority Claims (1)
JP 2023-026292 · Feb 22, 2023 · national
Continuity (1)
Related Publication 20240283437A1 · Aug 22, 2024
References Cited (4)
US 6556407B2 · Brando et al. · 2003 [cited by applicant]
US 7362147B2 · Rebholz-Goldmann · 2008 [cited by examiner]
US 10116292B2 · Yokoi et al. · 2018 [cited by applicant]
JP 2006129593A · 2006 [cited by applicant]