Granted Patent B2

US 12,593,396 · App. 18/451,477 · Granted Mar 31, 2026

Inventors: Mike Sapozhnikov (San Jose, CA); Amendra Koul (San Francisco, CA); David Nozadze (San Jose, CA); Joel Richard Goergen (Soulsbyville, CA); Upen Reddy Kareti (Union City, CA); Sayed Ashraf Mamun (San Jose, CA)

Assignee: CISCO TECHNOLOGY, INC.

H05K1/0251H05K1/0222H05K2201/0939H05K2201/09481H05K2201/09609

Abstract

Claims (24)

1 . An apparatus, comprising:

a layer of a printed circuit board (PCB);

a signal via extending through the layer, wherein the signal via is configured to transmit a signal therethrough;

a capacitive structure connected to the signal via at the layer, wherein the capacitive structure is electrically separate from each other component of the PCB at the layer;

an additional layer of the PCB;

a trace routed along the additional layer;

a pad connected to the signal via at the additional layer, wherein the pad is connected to the trace to electrically couple the signal via and the pad to one another; and

a plurality of ground vias positioned at the additional layer and within a threshold distance of the signal via, wherein a quantity of the plurality of ground vias is greater than a threshold quantity.

2 . The apparatus of claim 1 , wherein the pad comprises an oval shape.

3 . The apparatus of claim 1 , wherein the plurality of ground vias collectively surround the pad.

4 . The apparatus of claim 1 , wherein the pad is connected to a first portion of the signal via, and the PCB comprises an interconnect connected to a second portion of the signal via.

5 . An apparatus comprising:

a plurality of layers of a printed circuit board (PCB); and

a via assembly comprising:

a signal via extending from a first layer of the plurality of layers to a second layer of the plurality of layers; and

a capacitive structure connected to the signal via between the first layer and the second layer, wherein the capacitive structure is physically separate from each other component of the PCB, and the capacitive structure is positioned along the signal via to limit a change in impedance of the via assembly from the first layer to the second layer within a threshold value.

6 . The apparatus of claim 5 , wherein the signal via is coupled to a first component of the first layer at a first portion of the via assembly, the signal via is coupled to a second component of the second layer at a second portion of the via assembly, and the capacitive structure is connected to the signal via such that a first impedance of the first portion of the via assembly is within a first threshold of a second impedance of the first component and a third impedance of the second portion of the via assembly is within a second threshold of a fourth impedance of the second component.

7 . The apparatus of claim 6 , wherein the capacitive structure is connected to the signal via such that a fifth impedance of the via assembly between the first portion and the second portion varies between the first impedance of the first portion and the third impedance of the second portion.

8 . The apparatus of claim 6 , comprising the first component and the second component, wherein the first component comprises a trace, and the second component comprises an interconnect.

9 . The apparatus of claim 5 , wherein the capacitive structure is connected to the signal via by capturing a perimeter of the signal via.

10 . The apparatus of claim 5 , wherein the capacitive structure includes a plate or pad configuration.

11 . The apparatus of claim 5 , wherein the signal via is coupled to a trace of the first layer, and the apparatus comprises a plurality of ground vias positioned at the first layer and within a threshold distance of the signal via.

12 . The apparatus of claim 11 , wherein a quantity of the plurality of ground vias is greater than a threshold quantity.

13 . The apparatus of claim 11 , wherein the signal via is coupled to the trace by way of a pad.

Assignments (1)

Continuity (2)

References Cited (21)