Semiconductor memory devices
A semiconductor device includes gate electrodes on a substrate and a memory channel structure extending through the gate electrodes. The gate electrodes are spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate. The memory channel structure extends in the vertical direction on the substrate. The memory channel structure includes a first filling pattern extending in the vertical direction, a channel on a sidewall of the first filling pattern, and a charge storage structure on a sidewall of the channel. The first filling pattern includes a material having a thermal conductivity equal to or more than about 100 W/m·K at a temperature of about 25° C.
1 . A semiconductor device comprising:
gate electrodes on a substrate, the gate electrodes being spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate; and
a memory channel structure extending through the gate electrodes in the vertical direction on the substrate,
wherein the memory channel structure includes:
a first filling pattern having a pillar shape extending in the vertical direction, the first filling patter being a single layer;
a channel on and contacting a sidewall a bottom surface of the first filling pattern; and
a charge storage structure on a sidewall of the channel, and
wherein the first filling pattern includes a material having a thermal conductivity equal to or more than 100 W/m·K at a temperature of −25° C.
2 . The semiconductor device of claim 1 , wherein the first filling pattern includes a 2-dimensional material.
3 . The semiconductor device of claim 1 , wherein the first filling pattern includes boron nitride (BN), aluminum nitride (AlN), and/or beryllium oxide (BeO).
4 . The semiconductor device of claim 1 , wherein the first filling pattern includes the material having a dielectric constant equal to or less than about 11.7.
5 . The semiconductor device of claim 1 , wherein the first filling pattern includes the material having a bandgap equal to or more than about 6 eV.
6 . The semiconductor device of claim 1 ,
wherein the semiconductor device further comprises a second filling pattern includes silicon oxide.
7 . The semiconductor device of claim 1 , further comprising a second filling pattern between the first filling pattern and the channel, the second filling pattern including silicon oxide.
8 . The semiconductor device of claim 1 , wherein the charge storage structure includes a tunnel insulation pattern, a charge storage pattern, and a blocking pattern sequentially stacked on the sidewall of the channel in a horizontal direction substantially parallel to the upper surface of the substrate.
9 . A semiconductor device comprising:
gate electrodes on a substrate, the gate electrodes being spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate; and
a memory channel structure extending through the gate electrodes in the vertical direction on the substrate,
wherein the memory channel structure includes:
a filling pattern structure extending in the vertical direction;
a channel on a sidewall of the filling pattern structure; and
a charge storage structure on a sidewall of the channel,
wherein the filling pattern structure includes:
a first filling pattern having a pillar shape and including a material having a thermal conductivity equal to or more than about 100 W/m·K at a temperature of 25° C., the first filling pattern being a single layer; and
a second filling pattern on and contacting an outer sidewall of the first filling pattern, the second filling pattern including a material having a thermal conductivity less than that of the first filling pattern,
wherein the second filling pattern has a cup-like shape and
wherein the channel contacts a sidewall of the second filling pattern.
10 . The semiconductor device of claim 9 ,
wherein the second filling pattern contacts a lower surface of the first filling pattern.
11 . The semiconductor device of claim 9 ,
wherein the first filling pattern includes boron nitride (BN), aluminum nitride (AlN), and/or beryllium oxide (BeO), and
wherein the second filling pattern includes silicon oxide.
12 . The semiconductor device of claim 9 , wherein the first filling pattern includes the material having a dielectric constant equal to or less than about 11.7.
13 . A semiconductor device comprising:
a gate electrode structure on a substrate, the gate electrode structure including gate electrodes spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate; and
a memory channel structure extending through the gate electrode structure in the vertical direction on the substrate; and
wherein the memory channel structure includes:
a first filling pattern extending in the vertical direction and having a cup-like shape;
a second filling pattern at contacts an inner sidewall of the first filling pattern and fills a central space formed by the first filling pattern;
a channel contacting an outer sidewall of the first filling pattern; and
a charge storage structure on a sidewall of the channel, and
wherein the first filling pattern includes a material having a thermal conductivity equal to or more than about 100 W/m·K at a temperature of −25° C.
14 . The semiconductor device of claim 13 , wherein the second filling pattern includes silicon oxide.
15 . The semiconductor device of claim 14 , wherein the first filling pattern includes the material having a dielectric constant equal to or less than about 11.7.
16 . The semiconductor device of claim 14 , wherein the first filling pattern includes boron nitride (BN), aluminum nitride (AlN), and/or beryllium oxide (BeO).
17 . The semiconductor device of claim 13 , wherein the second filling pattern has a pillar shape.
18 . The semiconductor device of claim 13 , wherein the first filling pattern is formed from a single material layer.