Semiconductor device including channel structure comprising different compositions
A semiconductor device includes an upper conductive line on a substrate, a channel structure adjacent the upper conductive line, a gate dielectric film between the channel structure and the upper conductive line, and a conductive contact pattern electrically connected to the channel structure. The channel structure includes a main channel portion including an oxide semiconductor layer having a first composition, and a channel contact portion between the main channel portion and the conductive contact pattern. The channel contact portion is in contact with the conductive contact pattern and includes a material having a second composition that is different from the first composition.
1 . A semiconductor device comprising:
an upper conductive line on a substrate;
a channel structure adjacent the upper conductive line;
a gate dielectric film between the channel structure and the upper conductive line; and
a conductive contact pattern electrically connected to the channel structure,
wherein the channel structure comprises:
a main channel portion comprising an oxide semiconductor layer having a first composition; and
a channel contact portion between the main channel portion and the conductive contact pattern, wherein the channel contact portion is in contact with the conductive contact pattern and comprises a material having a second composition that is different from the first composition.
2 . The semiconductor device of claim 1 , wherein the channel contact portion and the oxide semiconductor layer respectively comprise one or more same elements, and the channel contact portion further comprises at least one dopant, wherein the at least one dopant comprises aluminum (Al), boron (B), arsenic (As), fluorine (F), or hydrogen (H).
3 . The semiconductor device of claim 1 , wherein an uppermost surface of the channel structure is closer to the substrate than an uppermost surface of the gate dielectric film, and wherein the gate dielectric film extends along a sidewall of conductive contact pattern.
4 . The semiconductor device of claim 1 , wherein the gate dielectric film comprises a dielectric film barrier liner in contact with the conductive contact pattern, and the dielectric film barrier liner comprises a metal oxide film comprising a dopant, wherein the dopant comprises aluminum (Al), boron (B), arsenic (As), fluorine (F), or hydrogen (H).
5 . The semiconductor device of claim 1 , wherein the oxide semiconductor layer of the main channel portion comprises indium gallium zinc oxide (InGaZnO or IGZO), tin-doped IGZO (Sn-IGZO), indium tungsten oxide (InWO or IWO), indium zinc oxide (InZnO or IZO), zinc tin oxide (ZnSnO or ZTO), zinc oxide (ZnO), yttrium-doped zinc oxide (YZO), indium gallium silicon oxide (InGaSiO or IGSO), indium (InO), tin oxide (SnO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), silicon indium zinc oxide (SiInZnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), or a combination thereof.
6 . The semiconductor device of claim 1 , wherein the conductive contact pattern comprises titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), or a combination thereof.
7 . The semiconductor device of claim 1 , further comprising:
a mold insulating pattern on the substrate, the mold insulating pattern having a sidewall defining a transistor region,
wherein the channel structure comprises a vertical channel portion extending along a vertical direction and in contact with the sidewall of the mold insulating pattern in the transistor region, and the channel contact portion is at an uppermost portion of the vertical channel portion relative to the substrate.
8 . The semiconductor device of claim 1 , further comprising:
a mold insulating pattern on the substrate, the mold insulating pattern having a sidewall defining a transistor region,
wherein the conductive contact pattern comprises surfaces in contact with a top surface and a sidewall of the channel contact portion, and a portion between the sidewall of the channel contact portion and the sidewall of the mold insulating pattern.
9 . The semiconductor device of claim 1 , further comprising:
a mold insulating pattern on the substrate, wherein the mold insulating pattern has a sidewall in contact with the conductive contact pattern, and
the sidewall of the mold insulating pattern comprises an inclined surface such that a distance between the sidewall of the mold insulating pattern and the gate dielectric film increases in a direction away from the substrate.
10 . The semiconductor device of claim 1 , further comprising:
a mold insulating pattern on the substrate, the mold insulating pattern comprising a sidewall facing the conductive contact pattern,
wherein the sidewall of the mold insulating pattern comprises a mold barrier liner in contact with the conductive contact pattern, and the mold barrier liner comprises an insulating film comprising a dopant, wherein the dopant comprises aluminum (Al), boron (B), arsenic (As), fluorine (F), or hydrogen (H).
11 . The semiconductor device of claim 1 , further comprising:
a lower conductive line between the substrate and the channel structure,
wherein the lower conductive line is spaced apart from the upper conductive line with the channel structure and the gate dielectric film therebetween in a vertical direction relative to the substrate and has a top surface in contact with the main channel portion,
the upper conductive line extends along a first lateral direction relative to the vertical direction, and
the lower conductive line extends along a second lateral direction that is perpendicular to the first lateral direction.
12 . The semiconductor device of claim 1 , further comprising:
a capacitor structure electrically connected to the conductive contact pattern.
13 . A semiconductor device comprising:
a plurality of lower conductive lines extending in parallel on a substrate;
a mold insulating pattern on the plurality of lower conductive lines, the mold insulating pattern defining a transistor region extending along a first lateral direction;
a plurality of channel structures aligned along the first lateral direction in the transistor region, each of the plurality of channel structures comprising a vertical channel portion extending along a sidewall of the mold insulating pattern;
an upper conductive line on the plurality of channel structures in the transistor region, the upper conductive line having a sidewall facing the vertical channel portion of each of the plurality of channel structures, the upper conductive line extending along the first lateral direction;
a gate dielectric film between the plurality of channel structures and the upper conductive line; and
a plurality of conductive contact patterns electrically connected to the vertical channel portions of the plurality of channel structures, respectively,
wherein the vertical channel portions of the plurality of channel structures respectively comprise:
a main channel portion in contact with a respective lower conductive line among the plurality of lower conductive lines, the main channel portion comprising an oxide semiconductor layer having a first composition; and
a channel contact portion between the main channel portion and a respective conductive contact pattern among the plurality of conductive contact patterns, wherein the channel contact portion is in contact with the respective conductive contact pattern and comprises a material having a second composition that is different from the first composition.
14 . The semiconductor device of claim 13 , wherein the transistor region includes a plurality of transistors comprising the plurality of channel structures, and
the plurality of transistors comprise first and second transistors adjacent one another in a second lateral direction that is perpendicular to the first lateral direction,
wherein a respective channel structure among the plurality of channel structures is shared between the first and second transistors.
15 . The semiconductor device of claim 13 , wherein the channel contact portion and the oxide semiconductor layer respectively comprise one or more same elements, and the channel contact portion further comprises at least one dopant, wherein the at least one dopant comprises aluminum (Al), boron (B), arsenic (As), fluorine (F), or hydrogen (H).
16 . The semiconductor device of claim 13 , wherein an uppermost surface of each of the plurality of channel structures is closer to the substrate than an uppermost surface of the gate dielectric film, and
each of the plurality of conductive contact patterns has a respective sidewall facing the gate dielectric film.
17 . The semiconductor device of claim 13 , wherein the gate dielectric film comprises a dielectric film barrier liner in contact with the respective conductive contact pattern,
the mold insulating pattern comprises a mold barrier liner in contact with the respective conductive contact pattern, and
each of the channel contact portion, the dielectric film barrier liner, and the mold barrier liner comprises at least one dopant, wherein the at least one dopant comprises aluminum (Al), boron (B), arsenic (As), fluorine (F), or hydrogen (H).
18 . The semiconductor device of claim 13 , wherein the oxide semiconductor layer of the main channel portion comprises indium gallium zinc oxide (InGaZnO or IGZO), tin-doped IGZO (Sn-IGZO), indium tungsten oxide (InWO or IWO), indium zinc oxide (InZnO or IZO), zinc tin oxide (ZnSnO or ZTO), zinc oxide (ZnO), yttrium-doped zinc oxide (YZO), indium gallium silicon oxide (InGaSiO or IGSO), indium (InO), tin oxide (SnO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), silicon indium zinc oxide (SiInZnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), or a combination thereof,
wherein the channel contact portion and the oxide semiconductor layer respectively comprise one or more same elements, and the channel contact portion further comprises at least one dopant, wherein the at least one dopant comprises aluminum (Al), boron (B), arsenic (As), fluorine (F), or hydrogen (H).
19 . A semiconductor device comprising:
a peripheral circuit region on a substrate, the peripheral circuit region comprising a plurality of peripheral circuits;
a lower conductive line on the peripheral circuit region, the lower conductive line being electrically connected to the plurality of peripheral circuits;
a mold insulating pattern on the lower conductive line, the mold insulating pattern having a sidewall defining a transistor region;
a channel structure in the transistor region, the channel structure comprising a bottom surface in contact with a top surface of the lower conductive line and a vertical channel portion adjacent the sidewall of the mold insulating pattern;
a gate dielectric film on the channel structure in the transistor region;
an upper conductive line on the gate dielectric film in the transistor region, the upper conductive line having a sidewall adjacent the vertical channel portion; and
a conductive contact pattern electrically connected to the vertical channel portion,
wherein the vertical channel portion of the channel structure comprises:
a main channel portion spaced apart from the conductive contact pattern, the main channel portion comprising an oxide semiconductor layer having a first composition; and
a channel contact portion in contact with the conductive contact pattern and comprising a material having a second composition that is different from the first composition.
20 . The semiconductor device of claim 19 , wherein the gate dielectric film comprises a dielectric film barrier liner in contact with the conductive contact pattern,
wherein the mold insulating pattern comprises a mold barrier liner in contact with the conductive contact pattern,
wherein the oxide semiconductor layer of the main channel portion comprises a first oxide semiconductor material of a first group, wherein the first group comprises indium gallium zinc oxide (InGaZnO or IGZO), tin-doped IGZO (Sn-IGZO), indium tungsten oxide (InWO or IWO), indium zinc oxide (InZnO or IZO), zinc tin oxide (ZnSnO or ZTO), zinc oxide (ZnO), yttrium-doped zinc oxide (YZO), indium gallium silicon oxide (InGaSiO or IGSO), indium (InO), tin oxide (SnO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), silicon indium zinc oxide (SiInZnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), or a combination thereof, and
wherein the channel contact portion comprises a second oxide semiconductor material of the first group and further comprises at least one dopant, wherein the at least one dopant comprises aluminum (Al), boron (B), arsenic (As), fluorine (F), or hydrogen (H), and
wherein each of the dielectric film barrier liner and the mold barrier liner comprises the at least one dopant.