IP Library › Granted Patent US 12,593,668
Granted Patent B2
US 12,593,668 · App. 17/807,006 · Granted Mar 31, 2026

Shallow and deep contacts with stitching

Inventors: Su Chen Fan (Cohoes, NY); Stuart Sieg (Albany, NY); Dominik Metzler (Clifton Park, NY); Indira Seshadri (Niskayuna, NY); Junli Wang (Slingerlands, NY)
Assignee: International Business Machines Corporation
H10W20/069H10P50/73H10P76/4085H10W20/056H10W20/084H10W20/089H10W20/42H10W20/435
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Quick Facts
Patent No.
US 12,593,668
App. No.
17/807,006
Granted
Mar 31, 2026
Kind
B2
Abstract

A semiconductor device is provided. The semiconductor device includes an interlayer dielectric layer; and a plurality of metal contacts formed in the interlayer dielectric layer. The plurality of metal contacts include a plurality of shallow metal contacts having a first depth, and a plurality of deep metal contacts having a second depth that is greater than the first depth, wherein a first one of the shallow metal contacts overlaps and directly contacts a first one of the deep metal contacts, and wherein the plurality of metal contacts have an equal spacing therebetween.

Claims (31)

1 . A semiconductor structure comprising:

an interlayer dielectric layer; and

a plurality of metal contacts formed in the interlayer dielectric layer, the plurality of metal contacts including

a plurality of shallow metal contacts having a first depth, and

a plurality of deep metal contacts having a second depth that is greater than the first depth,

wherein a first one of the shallow metal contacts overlaps and directly contacts a top surface of a first one of the deep metal contacts to form a combined contact, and

wherein a distance between the combined contact and immediately adjacent metal contacts is the same as a distance between adjacent shallow metal contacts.

2 . The semiconductor structure of claim 1 , wherein the first one of the shallow metal contacts has a width that is greater than a width of the first one of the deep metal contacts.

3 . The semiconductor structure of claim 1 , wherein at least a second one of the shallow metal contacts has a width that is different than a third one of the shallow metal contacts.

4 . The semiconductor structure of claim 1 , wherein at least a second one of the shallow metal contacts has a width that is the same as a third one of the shallow metal contacts.

5 . The semiconductor structure of claim 1 , each of the deep metal contacts has the same width.

6 . The semiconductor structure of claim 1 , wherein at least a second one of the shallow metal contacts has a width that is the same as at least a second one of the deep metal contacts.

7 . The semiconductor structure of claim 1 , wherein the first one of the shallow metal contacts and the first one of the deep metal contacts are formed as a single layer.

8 . The semiconductor structure of claim 1 , further comprising a metallic spacer layer formed between the plurality of metal contacts.

9 . The semiconductor structure of claim 8 , wherein the metallic spacer layer defines the equal spacing between the plurality of metal contacts.

10 . The semiconductor structure of claim 1 , wherein at least the first one of the deep metal contacts is electrically connected to a BEOL layer.

11 . A method of manufacturing a semiconductor structure, the method comprising:

forming a plurality of metal contacts in an interlayer dielectric layer, the plurality of metal contacts including

a plurality of shallow metal contacts having a first depth, and

a plurality of deep metal contacts having a second depth that is greater than the first depth,

wherein a first one of the shallow metal contacts overlaps and directly contacts a top surface of a first one of the deep metal contacts to form a combined contact, and

wherein a distance between the combined contact and immediately adjacent metal contacts is the same as a distance between adjacent shallow metal contacts.

12 . The method of manufacturing the semiconductor structure of claim 11 , wherein the first one of the shallow metal contacts has a width that is greater than a width of the first one of the deep metal contacts.

13 . The method of manufacturing the semiconductor structure of claim 11 , wherein at least a second one of the shallow metal contacts has a width that is different than a third one of the shallow metal contacts.

14 . The method of manufacturing the semiconductor structure of claim 11 , wherein at least a second one of the shallow metal contacts has a width that is the same as a third one of the shallow metal contacts.

15 . The method of manufacturing the semiconductor structure of claim 11 , each of the deep metal contacts has the same width.

16 . The method of manufacturing the semiconductor structure of claim 11 , wherein at least a second one of the shallow metal contacts has a width that is the same as at least a second one of the deep metal contacts.

17 . The method of manufacturing the semiconductor structure of claim 11 , wherein the first one of the shallow metal contacts and the first one of the deep metal contacts are formed as a single layer.

18 . The method of manufacturing the semiconductor structure of claim 11 , further comprising forming a metallic spacer layer above and surrounding at least one of the plurality of metal contacts.

19 . The method of manufacturing the semiconductor structure of claim 18 , wherein the metallic spacer layer defines the equal spacing between the plurality of metal contacts.

20 . The method of manufacturing the semiconductor structure of claim 18 , further comprising removing the metallic spacer layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2022
From: FAN, SU CHEN; SIEG, STUART; METZLER, DOMINIK; SESHADRI, INDIRA; WANG, JUNLI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 060210/0974 →
Continuity (1)
Related Publication 20230411212A1 · Dec 21, 2023
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