IP Library › Granted Patent US 12,593,695
Granted Patent B2
US 12,593,695 · App. 18/060,574 · Granted Mar 31, 2026

Structure and process for warpage reduction

Inventors: Hong Seung Yeon (Chandler, AZ); Liang He (Chandler, AZ); Whitney Bryks (Tempe, AZ); Jung Kyu Han (Chandler, AZ); Gang Duan (Chandler, AZ)
Assignee: INTEL CORPORATION
H01L23/562H01L24/13H01L2224/32225H01L2924/3511
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Quick Facts
Patent No.
US 12,593,695
App. No.
18/060,574
Granted
Mar 31, 2026
Kind
B2
Abstract

The present disclosure is directed to a semiconductor carrier platform having a support panel with a top surface and a bottom surface, with the top surface providing a working surface for assembling IC packages using panel-level packaging technology. In an aspect, a backside molding layer may be positioned on the bottom surface of the support panel to prevent or correct any panel warpage. In another aspect, a removable film may be positioned between the bottom surface of the support panel and the backside molding layer to allow the support panel to be readily cleaned and reused.

Claims (38)

1 . A semiconductor carrier platform comprising:

a support panel with a top surface and a bottom surface, wherein the top surface provides an active or working surface for integrated-circuit packages;

a backside molding layer, wherein the backside molding layer is positioned on the bottom surface of the support panel and has a coefficient of thermal expansion that is selected based on a coefficient of thermal expansion for the integrated-circuit packages to enable warpage control; and

a removable film positioned between the bottom surface of the support panel and the backside molding layer.

2 . The semiconductor carrier platform of claim 1 , wherein the backside molding layer further comprises an epoxy material.

3 . The semiconductor carrier platform of claim 1 , wherein the backside molding layer further comprises a molded material that is the same or similar to a mold material used in the integrated-circuit packages.

4 . The semiconductor carrier platform of claim 1 , wherein the support panel further comprises the backside molding layer being sized to be at least co-extensive with an active area of the support panel.

5 . A method comprising:

providing a support panel, wherein the support panel has a top surface and a bottom surface and the top surface provides an active area for assembly of integrated-circuit packages;

placing a removable film on the bottom surface of the support panel; and

depositing an epoxy material on the removable film to form a semiconductor carrier platform, wherein the epoxy material provides a backside molding layer for the semiconductor carrier platform that enables warpage control.

6 . The method of claim 5 , wherein the deposition of the epoxy material further comprises using a lamination, spray coating, slit coating, spin coating, or molding process.

7 . The method of claim 5 , further comprising providing the backside molding layer with a level working surface.

8 . The method of claim 7 , wherein the level working surface for the backside molding layer is provided by chemical-mechanical polishing.

9 . The method of claim 5 , wherein the backside molding layer has a thickness that is selected based on a thickness of the integrated-circuit packages.

10 . The method of claim 5 , wherein the backside molding layer enables warpage control by having a coefficient of thermal expansion that is selected based on a coefficient of thermal expansion for the integrated-circuit packages.

11 . The method of claim 5 , further comprising:

removing the removable film and the backside molding layer;

removing the integrated-circuit packages from the support panel; and

re-using the support panel,

wherein removing the removable film comprises using a mechanical debonding process, wherein the backside molding layer is simultaneously removed with the removable film.

12 . A method comprising:

providing a support panel, wherein the support panel has a top surface and a bottom surface;

providing a plurality of integrated-circuit packages on an active area of the top surface of the support panel;

depositing an epoxy material over the bottom surface, wherein the epoxy material provides a backside molding layer for the support panel; and

performing semiconductor processing operations on the plurality of integrated-circuit packages, wherein the support panel and the backside molding layer provide a semiconductor carrier platform for integrated-circuit packages during the semiconductor processing operations, wherein the backside molding layer has a coefficient of thermal expansion that is selected based on a coefficient of thermal expansion for the integrated-circuit packages to enable warpage control.

13 . The method of claim 12 , wherein the deposition of the epoxy material further comprises using a lamination, spray coating, slit coating, spin coating, or molding process.

14 . The method of claim 12 , further comprising:

placing a removable film on the bottom surface of the support panel, wherein the backside molding layer is deposited on the removable film.

15 . The method of claim 14 , further comprising:

removing the removable film and the backside molding layer;

removing the plurality of integrated-circuit packages from the support panel; and

re-using the support panel.

16 . The method of claim 15 , wherein the removable film comprises a low adhesion tape that is removed from the support panel using a peeling process, wherein the backside molding layer is simultaneously removed with the removable film.

17 . The method of claim 15 , wherein removing the removable film comprises using a mechanical debonding process, wherein the backside molding layer is simultaneously removed with the removable film.

18 . The method of claim 15 , wherein removing the removable film comprises using a thermal debonding process, wherein the backside molding layer is simultaneously removed with the removable film.

19 . The method of claim 15 , wherein removing the removable film comprises using a chemical debonding process, wherein the backside molding layer is simultaneously removed with the removable film.

20 . The method of claim 15 , wherein removing the removable film comprises using a laser debonding process, wherein the backside molding layer is simultaneously removed with the removable film.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 1, 2022
From: YEON, HONG SEUNG; HE, LIANG; BRYKS, WHITNEY; HAN, JUNG KYU; DUAN, GANG
To: INTEL CORPORATION
Reel/Frame 061934/0219 →
Continuity (1)
Related Publication 20240186263A1 · Jun 6, 2024
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