Prefetch aware LRU cache replacement policy
Prefetch aware LRU cache replacement policy is described. An example of an apparatus includes one or more processors including a graphic processor, the graphics processor including a load store cache having multiple cache lines (CLs), each including bits for a cache line level (CL level) and one or more sectors for data storage; wherein the graphics processor is to receive one or more data elements for storage in the cache; set a CL level to track each CL receiving data, including setting CL level 1 for a CL receiving data in response to a miss in the cache and setting a CL level 2 for a CL receiving prefetched data in response to a prefetch request, and, upon determining that space is required in the cache to store data, apply a cache replacement policy, the policy being based at least in part on set CL levels for the CLs.
1 . An apparatus comprising:
processing circuitry including graphics processing circuitry, the graphics processing circuitry including a load store cache, the load store cache including a plurality of cache lines, each of the plurality of cache lines including a plurality of bits for a cache line level (CL level) and one or more sectors for storage of data; and
memory for storage of data including data for graphics processing;
wherein the graphics processing circuitry is further to:
receive data for storage in the load store cache,
set a CL level to track each cache line receiving data, including setting CL level 1 for a cache line receiving data in response to a miss in the load store cache and setting a CL level 2 for a cache line receiving prefetched data in response to a prefetch request, and
upon determining that space is required in the load store cache to store additional data, apply a cache replacement policy, the cache replacement policy being based at least in part on set CL levels for the cache lines.
2 . The apparatus of claim 1 , wherein, in response to an increase in cache pressure, the graphics processing circuitry is further to decrement the set CL level for each cache line, the decrementing including reducing each instance of CL level 1 to CL level 0 and reducing each instance of CL level 2 to CL level 1.
3 . The apparatus of claim 1 , wherein the graphics processing circuitry is further to:
operate the cache replacement policy for the load store cache with either two CL levels or three CL levels based on a received selection.
4 . The apparatus of claim 1 , wherein the plurality of bits of each cache line includes two bits to encode at least three CL levels.
5 . The apparatus of claim 1 , wherein the plurality of bits for each cache line include a first bit to indicate whether the cache line contains prefetched data and a second bit to indicate whether the cache line is used.
6 . The apparatus of claim 1 , wherein the graphics processing circuitry is further to:
reissue a first prefetch request for a first data stored in a first cache line; and
set or reset the CL level of the first cache line to CL level 2 in response to the reissue of the first prefetch request.
7 . The apparatus of claim 1 , wherein the graphics processing circuitry is further to:
receive a first data in a first sector of a first cache line in response to a first prefetch request, the first cache line including at least the first sector and a second sector;
receive a second data in the second sector of the first cache line in response to a second prefetch request; and
set or reset the CL level of the first cache line to CL level 2 in response to receipt of the second data.
8 . The apparatus of claim 1 , wherein the graphics processing circuitry is to process a machine learning application, the machine learning application including prefetching of data to the load store cache for processing.
9 . At least one non-transitory computer-readable medium having stored thereon instructions which, when executed, cause a computing device to perform operations comprising:
receiving data for storage in a load store cache of a graphics processor in a computing system, the load store cache including a plurality of cache lines, each of the plurality of cache lines including a plurality of bits for a cache line level (CL level) and one or more sectors for storage of data;
setting a CL level to track each cache line receiving data, including setting CL level 1 for a cache line receiving data in response to a miss in the load store cache and setting a CL level 2 for a cache line receiving prefetched data in response to a prefetch request; and
upon determining that space is required in the load store cache to store additional data, applying a cache replacement policy, the cache replacement policy being based at least in part on set CL levels for the cache lines.
10 . The non-transitory computer-readable medium of claim 9 , wherein the operations further comprise:
in response to an increase in cache pressure, decrementing the set CL level for each cache line, the decrementing including reducing each instance of CL level 1 to CL level 0 and reducing each instance of CL level 2 to CL level 1.
11 . The non-transitory computer-readable medium of claim 9 , wherein the operations further comprise:
operating the cache replacement policy for the load store cache with either two CL levels or three CL levels based on a received selection.
12 . The non-transitory computer-readable medium of claim 9 , wherein the plurality of bits of each cache line includes two bits to encode at least three CL levels.
13 . The non-transitory computer-readable medium of claim 12 , wherein the plurality of bits for each cache line include a first bit to indicate whether the cache line contains prefetched data and a second bit to indicate whether the cache line is used.
14 . The non-transitory computer-readable medium of claim 9 , wherein the operations further comprise:
reissuing a first prefetch request for a first data stored in a first cache line; and
setting or resetting the CL level of the first cache line to CL level 2 in response to the reissue of the first prefetch request.
15 . The non-transitory computer-readable medium of claim 9 , wherein the operations further comprise:
receiving a first data in a first sector of a first cache line in response to a first prefetch request, the first cache line including at least the first sector and a second sector;
receiving a second data in the second sector of the first cache line in response to a second prefetch request; and
setting or resetting the CL level of the first cache line to CL level 2 in response to receipt of the second data.
16 . The non-transitory computer-readable medium of claim 9 , wherein the operations further comprise:
processing a machine learning application, the machine learning application including prefetching of data to the load store cache for processing.
17 . A method comprising:
receiving data for storage in a load store cache of a graphics processor in a computing system, the load store cache including a plurality of cache lines, each of the plurality of cache lines including a plurality of bits for a cache line level (CL level) and one or more sectors for storage of data;
setting a CL level to track each cache line receiving data, including setting CL level 1 for a cache line receiving data in response to a miss in the load store cache and setting a CL level 2 for a cache line receiving prefetched data in response to a prefetch request; and
upon determining that space is required in the load store cache to store additional data, applying a cache replacement policy, the cache replacement policy being based at least in part on set CL levels for the cache lines.
18 . The method of claim 17 , further comprising:
in response to an increase in cache pressure, decrementing the set CL level for each cache line, the decrementing including reducing each instance of CL level 1 to CL level 0 and reducing each instance of CL level 2 to CL level 1.
19 . The method of claim 17 , further comprising:
operating the cache replacement policy for the load store cache with either two CL levels or three CL levels based on a received selection.
20 . The method of claim 17 , wherein the plurality of bits of each cache line includes two bits to encode at least three CL levels.
21 . The method of claim 20 , wherein the plurality of bits for each cache line include a first bit to indicate whether the cache line contains prefetched data and a second bit to indicate whether the cache line is used.
22 . The method of claim 17 , further comprising:
reissuing a first prefetch request for a first data stored in a first cache line; and
setting or resetting the CL level of the first cache line to CL level 2 in response to the reissue of the first prefetch request.
23 . The method of claim 17 , further comprising:
receiving a first data in a first sector of a first cache line in response to a first prefetch request, the first cache line including at least the first sector and a second sector;
receiving a second data in the second sector of the first cache line in response to a second prefetch request; and
setting or resetting the CL level of the first cache line to CL level 2 in response to receipt of the second data.