Circuit analysis method, circuit analysis device, and circuit analysis system
Provided are a circuit analysis method, a circuit analysis device, and a circuit analysis system. An embodiment provides a circuit analysis method, including: building a circuit graph based on a netlist of a circuit; defining a node in the circuit graph; extracting an X (unknown) event for each node based on a waveform built as a result of simulation for the node; building an X event node from the X event that was extracted; building an X event graph by linking the X event node to at least one other X event node; traversing the X event graph and identifying a source X event and an involvement X event; and finding an X propagation path for the X event node, the X propagation path comprising the source X event and the involvement X event.
1 . A circuit analysis method, comprising:
executing, by a processor, computer readable program instructions embodied in a non-transitory memory to perform operations comprising:
building a circuit graph based on a netlist of a circuit;
defining a node in the circuit graph;
extracting an X event for the node based on a waveform built as a result of simulation for the node;
building an X event node from the X event that was extracted;
building an X event graph by linking the X event node to at least one other X event node;
traversing the X event graph and identifying a source X event and an involvement X event; and
finding an X propagation path for the X event node, the X propagation path comprising the source X event and the involvement X event.
2 . The circuit analysis method of claim 1 , wherein the building of the circuit graph comprises:
building the circuit graph represented at a gate level based on a logic gate having an input node and an output node based on the netlist of the circuit described at a transistor level based on transistors connected to the input node and the output node.
3 . The circuit analysis method of claim 2 , wherein the building of the circuit graph further comprises:
configuring the logic gate, in the netlist of the circuit, by inferring an input/output relationship between the transistors and by identifying a channel connected block (CCB) comprising an electrical block in which channel terminals are electrically connected to each other.
4 . The circuit analysis method of claim 1 , wherein the extracting of the X event comprises:
extracting a section in which the X event has occurred from the waveform.
5 . The circuit analysis method of claim 1 , wherein the building of the X event graph comprises:
linking the X event node to the at least one other X event node comprising a cause X event node that causes the X event of the X event node to occur.
6 . The circuit analysis method of claim 5 , wherein the cause X event node is identified by whether there is a preceding X event for the X event node in which the X event has occurred.
7 . The circuit analysis method of claim 5 , wherein the X event comprises a plurality of X events that were extracted, and wherein the linking of the X event node and the cause X event node is performed for all of the X events that were extracted.
8 . The circuit analysis method of claim 1 , wherein the identifying of the source X event and the involvement X event comprises:
traversing the X event graph according to a depth first search (DFS) algorithm.
9 . The circuit analysis method of claim 8 , wherein the traversing of the X event graph comprises:
performing a traversal according to the DFS algorithm for the X event node, wherein the X event node has no input in the X event graph.
10 . The circuit analysis method of claim 1 , further comprising:
generating a report comprising an analysis result for the source X event, the involvement X event, and the X propagation path.
11 . A circuit analysis device, comprising:
a circuit graph building module configured to build a circuit graph based on a netlist of a circuit;
an X event extracting module configured to extract an X event based on a waveform built as a result of simulation for a node defined in the circuit graph;
an X event linking module configured to build an X event node from the X event that was extracted, and link the X event node to at least one other X event node to build an X event graph;
a graph traversing module configured to traverse the X event graph and identify a source X event and an involvement X event; and
an X path finding module configured to find an X propagation path for the X event node, the X propagation path comprising the source X event and the involvement X event.
12 . The circuit analysis device of claim 11 , wherein the circuit graph building module is configured to build the circuit graph represented at a gate level based on a logic gate having an input node and an output node based on the netlist of the circuit described at a transistor level based on transistors connected to the input node and the output node.
13 . The circuit analysis device of claim 12 , wherein the circuit graph building module is further configured to configure a gate, in the netlist of the circuit, by inferring an input/output relationship between transistors and by identifying a channel connected block (CCB) comprising an electrical block in which channel terminals are electrically connected to each other.
14 . The circuit analysis device of claim 11 , wherein the X event extracting module is configured to extract a section in which the X event has occurred from the waveform.
15 . The circuit analysis device of claim 11 , wherein the X event linking module is configured to
link the X event node to the at least one other X event node comprising a cause X event node that causes the X event of the X event node to occur.
16 . The circuit analysis device of claim 15 , wherein the cause X event node is identified by whether there is a preceding X event for the X event node in which the X event has occurred.
17 . The circuit analysis device of claim 15 , wherein the X event comprises a plurality of X events that were extracted, and wherein
the linking of the X event node and the cause X event node is performed for all of the X events that were extracted.
18 . The circuit analysis device of claim 11 , wherein the graph traversing module is configured to traverse the X event graph according to a depth first search (DFS) algorithm.
19 . The circuit analysis device of claim 18 , wherein
the graph traversing module is further configured to
perform a traversal according to the DFS algorithm for the X event node, wherein the X event node has no input in the X event graph.
20 . A circuit analysis system, comprising:
a netlist database configured to store a netlist of a circuit;
a simulation database configured to store a waveform built as a result of simulation for a node defined in the circuit; and
a circuit analyzing device, wherein the circuit analyzing device comprises:
a circuit graph building module configured to build a circuit graph based on the netlist from the netlist database;
an X event extracting module configured to extract an X event for the node based on the waveform from the simulation database;
an X event linking module configured to build an X event node from the X event that was extracted, and configured to link the X event node to at least one other X event node to build an X event graph;
a graph traversing module configured to traverse the X event graph and configured to identify a source X event and an involvement X event; and
an X path finding module configured to find an X propagation path for the X event node, the X propagation path comprising the source X event and the involvement X event.