Systems and methods for powering driver circuitry

1 . A method for powering driver circuitry for an upper transistor of a half-bridge switching stage, comprising:

selectively charging, by a charging control circuit, a boot-strap capacitor by applying a first voltage source to the boot-strap capacitor when a voltage at the boot-strap capacitor is less than a first threshold, and disconnecting the first voltage source to the boot-strap capacitor when the voltage at the boot-strap capacitor exceeds a second threshold, such that the voltage at the boot-strap capacitor remains within a predetermined voltage range between the first threshold and the second threshold;

clamping, by a clamping circuit, the voltage at the boot-strap capacitor to prevent the voltage at the boot-strap capacitor from exceeding a predetermined maximum value, wherein the clamping circuit clamps the voltage at the boot-strap capacitor independent of the charging of the charging control circuit; and

electrically powering the driver circuitry at least partially via the boot-strap capacitor to drive the upper transistor of the half-bridge switching stage; and

electrically powering the upper transistor of the half-bridge switching stage by applying a second voltage source to the upper transistor of the half-bridge switching stage, the second voltage source being separate from the first voltage source of the charging control circuitry and the clamping circuit.

2 . The method of claim 1 , wherein selectively charging the boot-strap capacitor via the first voltage source comprises closing a switch electrically coupling the first voltage source to the boot-strap capacitor in response to the voltage at the boot-strap capacitor crossing a first threshold value.

3 . The method of claim 2 , wherein selectively charging the boot-strap capacitor via the first voltage source further comprises opening the switch electrically coupling the first voltage source to the boot-strap capacitor in response to the voltage at the boot-strap capacitor crossing a second threshold value.

4 . The method of claim 3 , wherein the second threshold value is greater than the first threshold value.

5 . The method of claim 1 , wherein clamping the voltage at the boot-strap capacitor comprises partially discharging the boot-strap capacitor in response to the voltage at the boot-strap capacitor crossing a threshold value.

6 . The method of claim 1 , further comprising charging the boot-strap capacitor via the second voltage source during power-up of a device including the half-bridge switching stage.

7 . The method of claim 6 , wherein a voltage magnitude of the second voltage source is less than a voltage magnitude of the first voltage source.

8 . The method of claim 1 , wherein:

the upper transistor comprises an upper field effect transistor (FET);

the boot-strap capacitor is electrically coupled between charging control circuitry and a source of the upper FET; and

the driver circuitry is configured to drive a gate of the upper FET.

9 . The method of claim 8 , wherein a voltage magnitude of the first voltage source is greater than a maximum gate-to-source voltage rating of the upper FET.

10 . The method of claim 8 , further comprising a current sense resistor electrically coupling the source of the upper FET to a terminal of the boot-strap capacitor.

11 . The method of claim 8 , where the upper FET is an n-channel FET.

12 . The method of claim 8 , wherein:

the half-bridge switching stage further includes a lower FET; and

a drain of the lower FET is electrically coupled to the source of the upper FET.

13 . A system for powering driver circuitry for an upper transistor of a half-bridge switching stage, comprising:

charging control circuitry configured to selectively charge a boot-strap capacitor of the half-bridge switching stage by applying a first voltage source to the boot-strap capacitor when a voltage at the boot-strap capacitor is less than a first threshold, and disconnecting the first voltage source to the boot-strap capacitor when the voltage at the boot-strap capacitor exceeds a second threshold, such that the voltage at the boot-strap capacitor remains within a predetermined voltage range between the first threshold and the second threshold; and

clamping circuitry configured to clamp the voltage at the boot-strap capacitor to prevent the voltage at boot-strap capacitor from exceeding a predetermined maximum value, wherein the clamping circuitry clamps the voltage at the boot-strap capacitor independent of the charging of the charging control circuitry,

wherein the driver circuitry is powered at least partially via the boot-strap capacitor to drive the upper transistor of the half-bridge switching stage, and

wherein the system is configured to electrically power the upper transistor of the half-bridge switching stage by applying a second voltage source separate from the first voltage source of the charging control circuitry and the clamping circuitry to the upper transistor of the half-bridge switching stage.

14 . The system of claim 13 , wherein the charging control circuitry comprises:

a switch configured to selectively electrically couple the boot-strap capacitor to the first voltage source; and

control circuitry configured to control the switch such that the switch closes and opens in response to the voltage at the boot-strap capacitor crossing first and second threshold values, respectively.

15 . The system of claim 13 , wherein the clamping circuitry comprises:

a discharge transistor configured to at least partially discharge the boot-strap capacitor; and control circuitry configured to activate the discharge transistor in response to the voltage at the boot-strap capacitor crossing a threshold value.

16 . A half-bridge switching stage, comprising:

an upper field effect transistor (FET) electrically coupled between a first node and a second node;

a lower field effect transistor electrically coupled between the second node and a third node;

driver circuitry configured to drive a gate of the upper FET;

a boot-strap capacitor electrically coupled to the second node and configured to at least partially power the driver circuitry;

charging control circuitry configured to selectively charge the boot-strap capacitor by applying a first voltage source to the boot-strap capacitor when a voltage at the boot-strap capacitor is less than a first threshold, and disconnecting the first voltage source to the boot-strap capacitor when the voltage at the boot-strap capacitor exceeds a second threshold, such that the voltage at the boot-strap capacitor remains within a predetermined voltage range between the first threshold and the second threshold; and

clamping circuitry configured to clamp the voltage at the boot-strap capacitor to prevent the voltage at the boot-strap capacitor from exceeding a predetermined maximum value, wherein the clamping circuitry clamps the voltage at the boot-strap capacitor independent of the charging of the charging control circuitry,

wherein the driver circuitry is powered at least partially via the boot-strap capacitor to drive the upper FET of the half-bridge switching stage, and

wherein the half-bridge switching stage is configured to electrically power the upper FET of the half-bridge switching stage by applying a second voltage source separate from the first voltage source of the charging control circuitry and the clamping circuitry to the upper FET of the half-bridge switching stage.

17 . The half-bridge switching stage of claim 16 , further comprising soft-start circuitry configured to charge the boot-strap capacitor via the second voltage source during power-up of a device including the half-bridge switching stage.

18 . The half-bridge switching stage of claim 16 , wherein the charging control circuitry comprises:

a switch configured to selectively electrically couple the boot-strap capacitor to the first voltage source; and

control circuitry configured to control the switch such that the switch closes and opens in response to the voltage at the boot-strap capacitor crossing first and second threshold values, respectively.

19 . The half-bridge switching stage of claim 16 , wherein:

a drain of the upper FET is electrically coupled to the first node;

a source of the upper FET is electrically coupled to the second node;

a drain of the lower FET is electrically coupled to the second node; and

a source of the lower FET is electrically coupled to the third node.

20 . The half-bridge switching stage of claim 16 , further comprising a current sense resistor electrically coupled between the second node and a fourth node, wherein the boot-strap capacitor is electrically coupled between the charging control circuitry and the fourth node.