Semiconductor device
A semiconductor device includes a substrate having an active cell region and an interfacial region adjacent to each other in a first direction, bit lines on the active cell region of the substrate that are spaced apart from each other in a second direction that intersects the first direction, and bit-line pads on the interfacial region of the substrate that are spaced apart from each other in the second direction. Each of the bit lines includes a first bit line and a second bit line that extend in the first direction and are spaced apart from each other in the second direction, a connection part that connects a first end of the first bit line to a second end of the second bit line, and a coupling part that connects one of the bit-line pads to one of the first bit line, the second bit line, and the connection part.
1 . A semiconductor device, comprising:
a substrate including an active cell region and an interfacial region, the active cell region and the interfacial region being adjacent to each other in a first direction;
bit lines on the active cell region of the substrate, the bit lines being spaced apart from each other in a second direction that intersects the first direction; and
bit-line pads on the interfacial region of the substrate, the bit-line pads being spaced apart from each other in the second direction,
wherein each of the bit lines includes:
a first bit line and a second bit line that extend in the first direction, the first bit line and the second bit line being spaced apart from each other in the second direction;
a connection part that connects a first end of the first bit line to a second end of the second bit line; and
a coupling part that connects one of the bit-line pads to one of the first bit line, the second bit line, and the connection part, and
wherein the first bit line, the second bit line, the connection part, and the coupling part are a single unitary piece.
2 . The semiconductor device as claimed in claim 1 , wherein:
the first end of the first bit line is opposite to a third end of the first bit line, the third end being directed toward the bit-line pads,
the second end of the second bit line is opposite to a fourth end of the second bit line, the fourth end being directed toward the bit-line pads, and
the coupling part connects the one of the bit-line pads to one of the third end of the first bit line and the fourth end of the second bit line.
3 . The semiconductor device as claimed in claim 2 , wherein the coupling part is connected to the third end of the first bit line in all of the bit lines.
4 . The semiconductor device as claimed in claim 2 , wherein:
one of the bit lines is configured such that the coupling part is connected to the third end of the first bit line, and
another of the bit lines that is adjacent to the one of the bit lines is configured such that the coupling part is connected to the fourth end of the second bit line.
5 . The semiconductor device as claimed in claim 2 , wherein each of the bit lines is positioned on one side in the first direction of the first bit line or is positioned on one side in the first direction of the second bit line.
6 . The semiconductor device as claimed in claim 1 , wherein:
the first end of the first bit line is directed toward the bit-line pads,
the second end of the second bit line is directed toward the bit-line pads, and
the coupling part connects the one of the bit-line pads to the connection part.
7 . The semiconductor device as claimed in claim 6 , wherein, when viewed in the second direction, each of the bit-line pads is between the first bit line and the second bit line of the bit lines.
8 . The semiconductor device as claimed in claim 1 , wherein the first bit line, the second bit line, and the connection part define a U shape, when viewed in a plan view.
9 . A semiconductor device, comprising:
a substrate including active cell regions and interfacial regions between the active cell regions, the active cell regions being arranged in a first direction;
bit lines on the active cell regions of the substrate, the bit lines extending in the first direction and being spaced apart from each other in a second direction that intersects the first direction; and
bit-line pads on the interfacial regions of the substrate, the bit-line pads being spaced apart from each other in the second direction,
wherein the active cell regions include:
outermost active cell regions on opposite sides in the first direction; and
central active cell regions between the outermost active cell regions, the central active cell regions being adjacent to each other in the first direction,
wherein the bit lines include:
first bit lines and second bit lines that are alternately arranged along the second direction on the outermost active cell regions; and
third bit lines and fourth bit lines that are alternately arranged along the second direction on the central active cell regions,
wherein a pair of neighboring ones of the first bit lines and the second bit lines are connected to each other through a connection part, the connection part extending between the pair of neighboring ones of the first bit lines and the second bit lines, and
wherein the third bit lines and the fourth bit lines are connected to different ones of the bit-line pads.
10 . The semiconductor device as claimed in claim 9 , wherein:
the first bit lines are connected to first ones of the bit-line pads, the first ones of the bit-line pads being adjacent to the first bit lines, and
the second bit lines are not directly connected to the bit-line pads.
11 . The semiconductor device as claimed in claim 10 , wherein the pair of neighboring ones of the first bit lines and the second bit lines are configured such that:
the connection part connects a first end of one of the first bit lines to a second end of one of the second bit lines;
the first end is opposite to a third end of the one of the first bit lines, the third end being directed toward the interfacial regions; and
the second end is opposite to a fourth end of the one of the second bit lines, the fourth end being directed toward the interfacial regions.
12 . The semiconductor device as claimed in claim 9 , wherein the connection part is connected to the bit-line pads adjacent to the connection part.
13 . The semiconductor device as claimed in claim 12 , wherein the connection part connects a third end of one of the first bit lines to a fourth end of one of the second bit lines, the third end and the fourth end facing toward the interfacial regions.
14 . The semiconductor device as claimed in claim 9 , wherein:
the third bit lines are connected to ones of the bit-line pads in the first direction of the third bit lines, and
the fourth bit lines are connected to ones of the bit-line pads in a direction opposite to the first direction of the fourth bit lines.
15 . The semiconductor device as claimed in claim 9 , further comprising word lines on the active cell regions of the substrate, the word lines extending in the second direction and being spaced apart from each other in the first direction, and a number of the word lines on each of the central active cell regions is twice a number of the word lines on each of the outermost active cell regions.
16 . The semiconductor device as claimed in claim 9 , wherein, when viewed in the first direction, a width of each of the outermost active cell regions is less than a width of each of the central active cell regions.
17 . A semiconductor device, comprising:
a substrate including an active cell region and an interfacial region, the active cell region and the interfacial region being adjacent to each other in a first direction;
word lines on the active cell region of the substrate, the word lines extending in a second direction that intersects the first direction and being spaced apart from each other in the first direction;
bit lines on the active cell region of the substrate, the bit lines extending in the first direction and being spaced apart from each other in the second direction; and
bit-line pads on the interfacial region of the substrate and spaced apart from each other in the second direction,
wherein, when viewed in a plan view, each of the bit lines has a U shape, each of the word lines twice crossing each of the bit lines, and
wherein each of the bit lines is connected to one of the bit-line pads.
18 . The semiconductor device as claimed in claim 17 ,
wherein each of the bit lines includes:
a first line that extends in the first direction;
a second line that extends in the first direction and is spaced apart in the second direction from the first line; and
a connection part that connects an end of the first line to an end of the second line, the end of the first line facing in a direction opposite to the first direction, and the end of the second line facing in the direction opposite to the first direction, and
wherein the first line of each of the bit lines extends onto the interfacial region and connects to a corresponding one of the bit-line pads.
19 . The semiconductor device as claimed in claim 17 ,
wherein each of the bit lines includes:
a first line that extends in the first direction;
a second line that extends in the first direction and is spaced apart in the second direction from the first line; and
a connection part that connects an end of the first line to an end of the second line, the end of the first line facing in the first direction, and the end of the second line facing in the first direction, and
wherein the connection part of the bit lines extends onto the interfacial region and connects to a corresponding one of the bit-line pads.