Multi-stack bitcell architecture
Various implementations described herein are related to a device having a memory architecture with a multi-stack of transistors that may be arranged in a multi-bitcell stack configuration. Also, the memory architecture may have a wordline that may be shared across the transistors of the multi-stack of transistors with each transistor coupled to a different bitline.
1 . A device comprising:
a memory architecture having a multi-stack of transistors arranged in a multi-bitcell stack configuration, and wherein a wordline is shared across the transistors of the multi-stack of transistors with each transistor coupled to a different bitline, wherein a global wordline is coupled to the wordline such that the global wordline is shared across the transistors.
2 . The device of claim 1 , wherein the transistors in the multi-stack of transistors are formed in the memory architecture as a three-dimensional (3D) memory structure.
3 . The device of claim 1 , wherein the multi-bitcell stack configuration has at least two transistors in the multi-stack of transistors.
4 . The device of claim 1 , wherein the multi-bitcell stack configuration has at least four transistors in the multi-stack of transistors.
5 . The device of claim 1 , wherein each transistor is coupled to ground or to its corresponding bitline of each different bitline.
6 . The device of claim 1 , wherein each different bitline is separated by an insulator.
7 . The device of claim 1 , wherein a global bitline is coupled to the different bitlines through local bitlines.
8 . A device comprising:
a memory architecture having a multi-stack of transistors arranged in a multi-bitcell stack configuration, and wherein a bitline is shared across the transistors of the multi-stack of transistors with each transistor coupled to a different wordline.
9 . The device of claim 8 , wherein the transistors in the multi-stack of transistors are formed in the memory architecture as a three-dimensional (3D) memory structure.
10 . The device of claim 8 , wherein the multi-bitcell stack configuration has at least two transistors in the multi-stack of transistors.
11 . The device of claim 8 , wherein the multi-bitcell stack configuration has at least four transistors in the multi-stack of transistors.
12 . The device of claim 8 , wherein each transistor is coupled to ground or to its corresponding bitline that is shared across the transistors.
13 . The device of claim 8 , wherein each different wordline is separated by an insulator.
14 . The device of claim 8 , wherein a different global wordline is coupled to each different wordline.
15 . A device comprising:
a memory architecture having a multi-stack of transistors arranged in a multi-bitcell stack configuration, and wherein a first wordline is shared across a first set of transistors of the multi-stack of transistors with each transistor in the first set of transistors coupled to a first set of shared bitlines, and wherein a second wordline is shared across a second set of transistors of the multi-stack of transistors with each transistor in the second set of transistors coupled to a second set of shared bitlines.
16 . The device of claim 15 , wherein the transistors in the multi-stack of transistors are formed in the memory architecture as a three-dimensional (3D) memory structure.
17 . The device of claim 15 , wherein the multi-bitcell stack configuration has at least four transistors in the multi-stack of transistors.
18 . The device of claim 15 , wherein each transistor is coupled to ground or to its corresponding bitline of the first set of bitlines and the second set of bitlines.
19 . The device of claim 15 , wherein the first wordline and the second wordline are separated by an insulator.
20 . The device of claim 15 , wherein a first global wordline is coupled to the first wordline such that the first global wordline is shared across the first set of transistors, and wherein a second global wordline is coupled to the second wordline such that the second global wordline is shared across the second set of transistors.