Bitcell architecture
Various implementations described herein are related to a device having multiple transistors that are arranged as a bitcell. The multiple transistors may include multiple P-type transistors that are arranged in a P-over-P stack configuration, and the multiple transistors may include multiple N-type transistors that are arranged in an N-over-N stack configuration.
1. A device comprising:
multiple transistors arranged as a bitcell;
wherein the multiple transistors include multiple P-type transistors that are sequentially arranged in a P-over-P stack configuration,
wherein the multiple transistors include multiple N-type transistors that are sequentially arranged in an N-over-N stack configuration, and
wherein the multiple P-type transistors in the P-over-P stack configuration are disposed alongside the multiple N-type transistors in the N-over-N stack configuration.
2. The device of claim 1 , wherein the multiple transistors are formed in a single monolithic semiconductor die.
3. The device of claim 2 , wherein:
the P-type transistors are arranged vertically in the P-over-P stack configuration,
the N-type transistors are arranged vertically in the N-over-N stack configuration, and
the multiple P-type transistors in the P-over-P stack configuration are disposed horizontally adjacent to the multiple N-type transistors in the N-over-N stack configuration within the single monolithic semiconductor die.
4. The device of claim 1 , wherein the multiple transistors are arranged as the bitcell for single-port memory applications, wherein the multiple transistors include six transistors (6T), and wherein the bitcell refers to a static random access memory (SRAM) bitcell.
5. The device of claim 1 , wherein the multiple transistors include field-effect transistors (FET) including P-type FET (PFET) and N-type FET (NFET).
6. The device of claim 1 , wherein:
the multiple P-type transistors include a pair of P-type transistors that are arranged in the P-over-P stack configuration, and
the multiple N-type transistors include a pair of N-type transistors that are arranged in the N-over-N stack configuration.
7. The device of claim 6 , wherein:
the pair of P-type transistors are cross-coupled with the pair of N-type transistors so as to provide two cross-coupled inverters that are utilized as a latch for the bitcell.
8. The device of claim 7 , wherein:
the pair of N-type transistors refer to a first pair of N-type transistors that are arranged in a first N-over-N stack configuration, and
the multiple N-type transistors include a second pair of N-type transistors that are arranged in a second N-over-N stack configuration.
9. The device of claim 8 , wherein:
the second pair of N-type transistors are utilized as a first passgate and a second passgate for the bitcell,
the first passgate is coupled between a first bitline and a first inverter of the two cross-coupled inverters, and
the second passgate is coupled between a second bitline and a second inverter of the two cross-coupled inverters.
10. The device of claim 1 , wherein:
the multiple transistors include P-type transistors and N-type transistors arranged in at least one of a P-over-N stack configuration and an N-over-P stack configuration, and
the multiple transistors having the P-over-P stack configuration, the N-over-N stack configuration, the P-over-N stack configuration and the N-over-P stack configuration are manufactured together in a single monolithic semiconductor die.
11. A bitcell comprising:
a pair of P-type devices sequentially arranged in a P-over-P stack configuration; and
a pair of N-type devices sequentially arranged in an N-over-N stack configuration,
wherein the pair of P-type transistors in the P-over-P stack configuration is disposed alongside the pair of N-type transistors in the N-over-N stack configuration, and
wherein the pair of P-type devices is cross-coupled with the pair of N-type devices so as to provide two cross-coupled inverters that are used as a latch for the bitcell.
12. The bitcell of claim 11 , wherein:
the pair of P-type transistors is arranged vertically in the P-over-P stack configuration,
the pair of N-type transistors is arranged vertically in the N-over-N stack configuration, and
the pair of P-type devices is disposed horizontally adjacent to the pair N-type devices within a single monolithic semiconductor die, and
the bitcell refers to a static random access memory (SRAM) bitcell for single-port memory applications.
13. The bitcell of claim 11 , wherein the pair of P-type devices refer to P-type field-effect transistor (PFET) devices, and wherein the pair of N-type devices refer to N-type field-effect transistor (NFET) devices.
14. The bitcell of claim 11 , wherein:
the pair of P-type devices refer to a pair of P-type transistors that are arranged in the P-over-P stack configuration, and
the pair of N-type devices refer to a first pair of N-type transistors that are arranged in a first N-over-N stack configuration.
15. The bitcell of claim 14 , further comprising:
another pair of N-type devices that refer to a second pair of N-type transistors that are arranged in a second N-over-N stack configuration.
16. The bitcell of claim 15 , wherein:
the second pair of N-type transistors are utilized as a first passgate and a second passgate for the bitcell,
the first passgate is coupled between a first bitline and a first inverter of the two cross-coupled inverters, and
the second passgate is coupled between a second bitline and a second inverter of the two cross-coupled inverters.
17. The bitcell of claim 11 , further comprising:
multiple devices including P-type devices and N-type devices arranged in at least one of a P-over-N stack configuration and an N-over-P stack configuration,
wherein the pair of P-type devices arranged in the P-over-P stack configuration, the pair of N-type devices arranged in the N-over-N stack configuration are manufactured together in a single monolithic semiconductor die along with the P-type devices and the N-type devices that are arranged in the P-over-N stack configuration and the N-over-P stack configuration.
18. A method comprising:
fabricating multiple devices that are arranged as a bitcell;
fabricating the multiple devices with a pair of P-type transistors that are sequentially arranged in a P-over-P stack configuration;
fabricating the multiple devices with a pair of N-type transistors that are sequentially arranged in an N-over-N stack configuration; and
cross-coupling the pair of P-type transistors with the pair of N-type transistors so as to provide two cross-coupled inverters that are used as a latch for the bitcell,
wherein the pair of P-type transistors in the P-over-P stack configuration is disposed alongside the pair of N-type transistors in the N-over-N stack configuration.
19. The method of claim 18 , further comprising:
fabricating the multiple devices with another pair of N-type transistors that are arranged in another N-over-N stack configuration,
wherein the another pair of N-type transistors are utilized as a first passgate and a second passgate for the bitcell,
wherein the first passgate is coupled between a first bitline and a first inverter of the two cross-coupled inverters, and
wherein the second passgate is coupled between a second bitline and a second inverter of the two cross-coupled inverters.
20. The method of claim 18 , further comprising:
fabricating multiple devices including P-type devices and N-type devices arranged in at least one of a P-over-N stack configuration and an N-over-P stack configuration,
wherein the pair of P-type transistors arranged in the P-over-P stack configuration, the pair of N-type transistors arranged in the N-over-N stack configuration are manufactured together in a single monolithic semiconductor die along with the P-type devices and the N-type devices that are arranged in the P-over-N stack configuration and the N-over-P stack configuration.