Voltage reference circuit and a power management unit
A voltage reference circuit comprises: first transistor, second transistor, first regulating transistor, and second regulating transistor arranged in a stacked connection, wherein first voltage is provided at first node between first and second transistor, second voltage is provided at second node between second transistor and first regulating transistor, third voltage is provided at third node between first and second regulating transistor; wherein first regulating transistor and second regulating transistor are connected to first node and second node, respectively, for compensating changes in first voltage and second voltage, respectively, to maintain stable voltage levels; wherein voltage reference circuit outputs at least one of the first, second or third voltage as a reference voltage.
1 . A voltage reference circuit comprising:
a first transistor comprising a gate terminal, a source terminal, and a drain terminal;
a second transistor comprising a gate terminal, a source terminal, and a drain terminal, wherein the first transistor and the second transistor are arranged in a stacked connection between a terminal connected to ground and a terminal connected to a supply voltage, wherein a first voltage is provided at a first node between the first transistor and the second transistor;
a first regulating transistor comprising a gate terminal, a source terminal, and a drain terminal, wherein the first regulating transistor is connected between the supply voltage and the first transistor in a stacked connection with the second transistor, wherein a second voltage is provided at a second node between the second transistor and the first regulating transistor, and wherein the first regulating transistor is connected to the first node for compensating changes in the first voltage at the first node to maintain a stable first voltage level;
a second regulating transistor comprising a gate terminal, a source terminal, and a drain terminal, wherein the second regulating transistor is connected between the supply voltage and the second transistor in a stacked connection with the first regulating transistor, wherein a third voltage is provided at a third node between the first regulating transistor and the second regulating transistor, and wherein the second regulating transistor is connected to the second node for compensating changes in the second voltage at the second node to maintain a stable second voltage level,
wherein the voltage reference circuit is configured to output at least one of the first voltage, the second voltage, or the third voltage as a reference voltage; and
at least one additional regulating transistor, wherein the first regulating transistor, the second regulating transistor and the at least one additional regulating transistor form a stack between the supply voltage and the second transistor, wherein an additional node is provided between each pair of regulating transistors in the stack and the additional node is connected to a regulating transistor immediately above the pair of regulating transistors in the stack for compensating changes in the voltage at the additional node.
2 . The voltage reference circuit according to claim 1 , wherein the first transistor, the second transistor, the first regulating transistor, and the second regulating transistor are all n-type metal-oxide-semiconductor, nMOS, transistors, and wherein a drain terminal of the first transistor is connected to a source terminal of the second transistor, a drain terminal of the second transistor is connected to a source terminal of the first regulating transistor and a drain terminal of the first regulating transistor is connected to a source terminal of the second regulating transistor, and wherein the first node is connected to the drain terminal of the first transistor and the source terminal of the second transistor, the second node is connected to the drain terminal of the second transistor and the source terminal of the first regulating transistor, and the third node is connected to the drain terminal of the first regulating transistor and the source terminal of the second regulating transistor.
3 . The voltage reference circuit according to claim 1 , wherein an aspect ratio of the first regulating transistor equals an aspect ratio of the second transistor.
4 . The voltage reference circuit according to claim 1 , wherein the voltage reference circuit is configured to output a reference voltage from a node having a largest voltage and being regulated by a regulating transistor.
5 . The voltage reference circuit according to claim 1 , wherein the voltage reference circuit is configured to output more than one reference voltage.
6 . The voltage reference circuit according to claim 1 , wherein each of the first transistor, the second transistor, the first regulating transistor and the second regulating transistor further comprises a bulk terminal, and wherein the first node is connected to the bulk terminal of the first regulating transistor, and the second node is connected to the bulk terminal of the second regulating transistor.
7 . The voltage reference circuit according to claim 6 , wherein the gate terminal of the second transistor is connected to the source terminal of the second transistor, the gate terminal of the first regulating transistor is connected to the source terminal of the first regulating transistor and the gate terminal of the second regulating transistor is connected to the source terminal of the second regulating transistor.
8 . The voltage reference circuit according to claim 6 , wherein the bulk terminal of the first transistor is connected to ground and wherein the bulk terminal of the second transistor is connected to ground.
9 . The voltage reference circuit according to claim 6 , wherein the first transistor, the second transistor, the first regulating transistor and the second regulating transistor are input/output transistors.
10 . The voltage reference circuit according to claim 1 , wherein the first node is connected to the gate terminal of the first regulating transistor, and the second node is connected to the gate terminal of the second regulating transistor.
11 . The voltage reference circuit according to claim 10 , wherein the gate terminal of the second transistor is connected to ground.
12 . The voltage reference circuit according to claim 10 , wherein the first transistor is an input/output transistor and wherein each of the second transistor, the first regulating transistor and the second regulating transistor is a native transistor, an oxide layer of the native transistor being thinner than an oxide layer of the input/output transistor.
13 . The voltage reference circuit according to claim 1 , wherein the first transistor, the second transistor, the first regulating transistor and the second regulating transistor are all configured to operate at a subthreshold region.
14 . The voltage reference circuit according to claim 1 , wherein the gate terminal of the first transistor is connected to the first node.
15 . A power management unit comprising the voltage reference circuit according to claim 1 , the power management unit being configured to produce a direct current, DC, voltage based on the reference voltage.
16 . A neural sensing apparatus comprising the power management unit according to claim 15 .
17 . A voltage reference circuit comprising:
a first transistor comprising a gate terminal, a source terminal, and a drain terminal;
a second transistor comprising a gate terminal, a source terminal, and a drain terminal, wherein the first transistor and the second transistor are arranged in a stacked connection between a terminal connected to ground and a terminal connected to a supply voltage, wherein a first voltage is provided at a first node between the first transistor and the second transistor;
a first regulating transistor comprising a gate terminal, a source terminal, and a drain terminal, wherein the first regulating transistor is connected between the supply voltage and the first transistor in a stacked connection with the second transistor, wherein a second voltage is provided at a second node between the second transistor and the first regulating transistor, and wherein the first regulating transistor is connected to the first node for compensating changes in the first voltage at the first node to maintain a stable first voltage level; and
a second regulating transistor comprising a gate terminal, a source terminal, and a drain terminal, wherein the second regulating transistor is connected between the supply voltage and the second transistor in a stacked connection with the first regulating transistor, wherein a third voltage is provided at a third node between the first regulating transistor and the second regulating transistor, and wherein the second regulating transistor is connected to the second node for compensating changes in the second voltage at the second node to maintain a stable second voltage level,
wherein the voltage reference circuit is configured to output at least one of the first voltage, the second voltage, or the third voltage as a reference voltage, and
wherein the first transistor, the second transistor, the first regulating transistor, and the second regulating transistor are all n-type metal-oxide-semiconductor, nMOS, transistors, and wherein a drain terminal of the first transistor is connected to a source terminal of the second transistor, a drain terminal of the second transistor is connected to a source terminal of the first regulating transistor and a drain terminal of the first regulating transistor is connected to a source terminal of the second regulating transistor, and wherein the first node is connected to the drain terminal of the first transistor and the source terminal of the second transistor, the second node is connected to the drain terminal of the second transistor and the source terminal of the first regulating transistor, and the third node is connected to the drain terminal of the first regulating transistor and the source terminal of the second regulating transistor.
18 . A voltage reference circuit comprising:
a first transistor comprising a gate terminal, a source terminal, and a drain terminal;
a second transistor comprising a gate terminal, a source terminal, and a drain terminal, wherein the first transistor and the second transistor are arranged in a stacked connection between a terminal connected to ground and a terminal connected to a supply voltage, wherein a first voltage is provided at a first node between the first transistor and the second transistor;
a first regulating transistor comprising a gate terminal, a source terminal, and a drain terminal, wherein the first regulating transistor is connected between the supply voltage and the first transistor in a stacked connection with the second transistor, wherein a second voltage is provided at a second node between the second transistor and the first regulating transistor, and wherein the first regulating transistor is connected to the first node for compensating changes in the first voltage at the first node to maintain a stable first voltage level;
a second regulating transistor comprising a gate terminal, a source terminal, and a drain terminal, wherein the second regulating transistor is connected between the supply voltage and the second transistor in a stacked connection with the first regulating transistor, wherein a third voltage is provided at a third node between the first regulating transistor and the second regulating transistor, and wherein the second regulating transistor is connected to the second node for compensating changes in the second voltage at the second node to maintain a stable second voltage level;
wherein the voltage reference circuit is configured to output at least one of the first voltage, the second voltage, or the third voltage as a reference voltage; and
wherein the gate terminal of the first transistor is connected to the first node.