Systems and methods for debugging multi-core processors with configurable isolated partitions
Systems and methods for debugging multi-core processors with configurable isolated partitions have been described. In an illustrative, non-limiting embodiment, an integrated circuit, may include: a plurality of Cross-Trigger Matrices (CTMs) configured to establish a debug network among a plurality of multi-cluster tiles (MCTs), where each MCT includes a plurality of processor cores, and where each processor core is assigned to a respective isolated partition of processor cores; and a System Interface (SI) coupled to the plurality of CTMs, where the SI is configured to control the plurality of CTMs to enable or disable at least a portion of the debug network to allow an isolated partition to be debugged independently of another isolated partition. A method may include enabling or disabling, by the SI, buses between the MCTs to create isolated debug networks, each isolated debug network corresponding to a distinct isolated partition of processor cores.
1 . An integrated circuit, comprising:
a plurality of multi-cluster tiles (MCTs), wherein each MCT is allocated to one of four quartiles and each MCT comprises:
a plurality of processor cores, wherein each processor core is assigned to a respective isolated partition of processor cores, from a plurality of isolated partitions; and
a cross-trigger matrix (CTM) communicatively coupled to the respective plurality of processor cores to transmit a trigger request to a particular isolated partition from the plurality of isolated partitions;
wherein, collectively, the CTMs from each MCT establish a debug network;
a System Interface (SI) coupled to each CTM, wherein the SI is configured to:
determine that a first MCT of the plurality of MCTs is in a first quartile of the four quartiles and includes a first set of processor cores in a first isolated partition out of the plurality of isolated partitions,
determine that a second MCT of the plurality of MCTs is in a second quartile of the four quartiles and includes a second set of processor cores in the first isolated partition out of the plurality of isolated partitions, and
control a first CTM of the first MCT and a second CTM of the second MCT to disable a portion of the debug network associated with the first isolated partition to allow an isolated partition to be debugged independently of another isolated partition.
2 . The integrated circuit of claim 1 , wherein the SI is configured to allow all processor cores within the respective isolated partition to be at least one of: halted, single-stepped, or interrogated, without affecting any operation of any other processor core of any other isolated partition.
3 . The integrated circuit of claim 1 , wherein the SI is configured to allow any processor cores within the respective isolated partition to receive a debug command without affecting any operation of any other processor core of any other isolated partition.
4 . The integrated circuit of claim 3 , wherein the debug command comprises at least one of: a break, a step, or a register dump command.
5 . The integrated circuit of claim 1 , wherein each isolated partition comprises a configuration of either 16, 32, 64, 128, or 256 processor cores of the plurality of processor cores, and wherein the SI is configured to allow any individual processor core within any individual isolated partition to be traced without regard to the configuration of the individual isolated partition.
6 . The integrated circuit of claim 1 , wherein each isolated partition comprises a configuration of either 16, 32, 64, 128, or 256 processor cores of the plurality of processor cores, wherein each isolated partition executes a plurality of virtual applications on its respective processor cores, and wherein the SI is configured to allow each of the virtual applications to be monitored for performance without regard to the configuration of the respective isolated partition.
7 . The integrated circuit of claim 1 , wherein the SI is configured to select the portion of the debug network based, at least in part, upon a configuration of the isolated partitions of processor cores.
8 . The integrated circuit of claim 1 , wherein the SI is configured to enable or disable the portion of the debug network at run-time.
9 . The integrated circuit of claim 1 , wherein the SI is configured to control the plurality of CTMs in response to an indication that the isolated partitions have been reconfigured.
10 . The integrated circuit of claim 9 , wherein the SI is configured to control another one or more of the plurality of CTMs to enable or disable at least another portion of the debug network to allow a reconfigured isolated partition to be debugged independently of another reconfigured isolated partition.
11 . The integrated circuit of claim 1 , wherein at least a given one of the plurality of isolated partitions enables a debugging of applications executed on processor cores of the given isolated partition.
12 . The integrated circuit of claim 11 , wherein the applications comprise virtual applications.
13 . A method, comprising:
receiving, at a System Interface (SI) of a hardware accelerator having a plurality of multi-cluster tiles (MCTs), wherein each MCT is allocated to one of four quartiles and comprises a plurality of processor cores and a dedicated cross-trigger matrix (CTM) communicatively coupled to the respective plurality of processor cores, an indication of configuration of a plurality of isolated partitions of processor cores;
determining, by the SI, that a first MCT of the plurality of MCTs is in a first quartile of the four quartiles and includes a first set of processor cores in a first isolated partition out of the plurality of isolated partitions;
determining, by the SI, that a second MCT of the plurality of MCTs is in a second quartile of the four quartiles and includes a second set of processor cores in the first isolated partition out of the plurality of isolated partitions; and
controlling a first CTM of the first MCT and a second CTM of the second MCT to disable a portion of a debug network associated with the first isolated partition by disabling, by the SI, one or more buses between two or more of the plurality of MCTs via the dedicated cross-trigger matrix to create a plurality of isolated debug networks, each isolated debug network corresponding to a distinct isolated partition of processor cores.
14 . The method of claim 13 , wherein the indication is received at run-time.
15 . The method of claim 13 , wherein the one or more buses include a router bus, a message bus, and a broadcast bus.
16 . The method of claim 13 , wherein enabling or disabling the one or more buses further comprises transmitting a signal, by the SI, to the dedicated CTM.
17 . A hardware accelerator, comprising:
an isolated partition control circuit coupled to a plurality of processor cores within multi-cluster tiles (MCTs), wherein each MCT is allocated to one set of a plurality of MCT sets, the isolated partition control circuit configured to dynamically partition the plurality of processor cores into a plurality of isolated partitions to prevent an application executed on one more processor cores of a first isolated partition from corrupting or interfering with another application executed on a different one or more processor cores of a second isolated partition; and
a System Interface (SI) configured to:
determine that a first MCT of the plurality of MCTs is in a first set of the plurality of sets and is associated with a first set of processor cores in a first isolated partition out of the plurality of isolated partitions,
determine that a second MCT of the plurality of MCTs is in a second set of the plurality of sets and includes a second set of processor cores in the first isolated partition out of the plurality of isolated partitions, and
control a first CTM of the first MCT and a second CTM of the second MCT to disable one or more buses between two or more of the plurality of MCTs to create a plurality of isolated debug networks wherein a portion of the plurality of isolated debug networks associated the first isolated portion is disabled, each isolated debug network corresponding to a distinct isolated partition.
18 . The hardware accelerator of claim 17 , further comprising a plurality of mesh routers coupled to the isolated partition control circuit, wherein the isolated partition control circuit is configured to use at least one of the plurality of mesh routers to enable or disable one or more other buses to dynamically partition the plurality of processor cores.
19 . The hardware accelerator of claim 18 , wherein the one or more other buses comprise at least one of: a router bus, a message bus, or a broadcast bus.