Secure debugging
Disclosed embodiments provide systems and methods that can be used as part of or in combination with autonomous navigation, autonomous driving, or driver assist technology features. As opposed to fully autonomous driving, driver assist technology may refer to any suitable technology to assist drivers in the navigation or control of their vehicles. In various embodiments, the system may include one or more cameras mountable in a vehicle and an associated processor that monitors the environment of the vehicle. In further embodiments, additional types of sensors can be mounted in the vehicle and can be used in the autonomous navigation or driver assist systems. These systems and methods may include the use of a shared cache that is shared by a group of processing units to improve analysis of images captured by the one or more cameras.
1 . An integrated circuit for secure debugging, the integrated circuit comprising:
a processing unit;
an access control unit;
a debug port configured to receive a debug request; and
a security unit configured to:
receive a debugging initiation request based on a trigger event;
determine a debugging enablement, the debugging enablement allowing the secure debugging of the processing unit after the debugging initiation request is received; and
prepare at least a part of the integrated circuit for the secure debugging responsive to the determination of the debugging enablement, wherein the preparing comprises validating that programs executed by the processing unit and not related to the secure debugging are terminated prior to the secure debugging;
wherein the access control unit is configured to allow the secure debugging of the processing unit responsive to completion of the preparation and upon receiving the debug request via the debug port; and
wherein the integrated circuit is configured to execute the secure debugging of the processing unit responsive to the allowance of the secure debugging.
2 . The integrated circuit of claim 1 , wherein the trigger event comprises a boot process of the integrated circuit.
3 . The integrated circuit of claim 1 , wherein the trigger event comprises a timeout period after a boot process of the integrated circuit has completed.
4 . The integrated circuit of claim 1 , wherein the trigger event comprises a signal indicating that secure debugging is needed based on a change of state of the integrated circuit.
5 . The integrated circuit of claim 4 , wherein the change of state of the integrated circuit comprises at least one of: a predefined behavior of the integrated circuit, a predefined behavior of a first unit that is affected by the integrated circuit, a software update of a second unit that is affected by the integrated circuit, or a new installation of the integrated circuit.
6 . The integrated circuit of claim 1 , wherein the security unit is configured to validate the debug request for the secure debugging.
7 . The integrated circuit of claim 6 , wherein the security unit is configured to validate that a debug requestor that generated the debug request is aware of a unique identifier of the processing unit.
8 . The integrated circuit of claim 1 , wherein the security unit is configured to retrieve boot instructions from a memory unit of the integrated circuit.
9 . The integrated circuit of claim 8 , wherein the determination of the debugging enablement is responsive to the retrieval of the boot instructions.
10 . The integrated circuit of claim 8 , wherein the security unit is configured to decrypt encrypted data stored in the memory unit of the integrated circuit, the decryption is based on a unique identifier of the processing unit.
11 . The integrated circuit of claim 10 , wherein the encrypted data includes debugging instructions.
12 . The integrated circuit of claim 1 , wherein the security unit is configured to generate a debugging determination indicator responsive to the determination of the debugging enablement, wherein the debugging determination indicator is accessible by the access control unit.
13 . The integrated circuit of claim 12 , wherein the debugging determination indicator can be changed only by the determination of the debugging enablement.
14 . The integrated circuit of claim 1 , wherein the security unit is configured to erase sensitive information from a memory unit accessible to the secure debugging.
15 . A method for a secure debugging of a processing unit of an integrated circuit, the method comprising:
receiving a debugging initiation request based on a trigger event;
determining a debugging enablement, the debugging enablement allowing the secure debugging of the processing unit after the debugging initiation request is received;
preparing at least a part of the integrated circuit for the secure debugging responsive to the determination of the debugging enablement, wherein the preparing comprises validating that programs executed by the processing unit and not related to the secure debugging are terminated prior to the secure debugging;
allowing, by an access control unit of the integrated circuit, the secure debugging of the processing unit responsive to completion of the preparation and upon receiving the debug request via a debug port of the integrated circuit; and
executing the secure debugging of the processing unit responsive to the allowance of the secure debugging.
16 . The method of claim 15 , wherein the trigger event comprises a boot process of the integrated circuit.
17 . The method of claim 15 , wherein the trigger event comprises a timeout period after a boot process of the integrated circuit has completed.
18 . The method of claim 15 , wherein the trigger event comprises a signal indicating that secure debugging is needed based on a change of state of the integrated circuit.
19 . The method of claim 18 , wherein the change of state of the integrated circuit comprises at least one of: a predefined behavior of the integrated circuit, a predefined behavior of a first unit that is affected by the integrated circuit, a software update of a second unit that is affected by the integrated circuit, or a new installation of the integrated circuit.
20 . At least one non-transitory machine-readable storage medium, comprising a plurality of instructions that, responsive to being executed with processor circuitry of a computer-controlled device, cause the computer-controlled device to:
receive a debugging initiation request based on a trigger event;
determine a debugging enablement, the debugging enablement allowing the secure debugging of the processing unit after the debugging initiation request is received;
prepare at least a part of the integrated circuit for the secure debugging responsive to the determination of the debugging enablement, wherein the preparing comprises validating that programs executed by the processing unit and not related to the secure debugging are terminated prior to the secure debugging;
allow, by an access control unit of the integrated circuit, the secure debugging of the processing unit responsive to completion of the preparation and upon receiving the debug request via a debug port of the integrated circuit; and
execute the secure debugging of the processing unit responsive to the allowance of the secure debugging.