IP Library Granted Patent US 12,604,752
Granted Patent B2
US 12,604,752 · App. 18/132,629 · Granted Apr 14, 2026

Semiconductor die package

Inventors: Edward Fürgut (Dasing, DE); Irmgard Escher-Poeppel (Duggendorf, DE); Martin Gruber (Schwandorf, DE); Ivan Nikitin (Regensburg, DE); Hans-Joachim Schulze (Taufkirchen, DE)
Assignee: Infineon Technologies Austria AG
H01L24/35H01L24/37H01L21/56H01L23/3107H01L23/485H01L23/495H01L24/03H01L24/04H01L24/05H01L24/06H01L2224/0312H01L2224/03442H01L2224/03502H01L2224/03848H01L2224/05575H01L2224/0558H01L2224/05582H01L2224/06181H01L2224/35848H01L2224/35986H01L2224/37005H01L2224/37011H01L2224/82101H01L2924/10272H01L2924/1033H01L2924/1301H01L2924/13055H01L2924/13091
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Quick Facts
Patent No.
US 12,604,752
App. No.
18/132,629
Granted
Apr 14, 2026
Kind
B2
Abstract

A semiconductor die package includes a semiconductor transistor die having a contact pad on an upper main face. The semiconductor die package also includes an electrical conductor disposed on the contact pad and fabricated by laser-assisted structuring of a metallic material, and an encapsulant covering the semiconductor die and at least a portion of the electrical conductor.

Claims (30)

1 . A semiconductor die package, comprising:

a semiconductor transistor die, the semiconductor transistor die comprising a contact pad on an upper main face;

an electrical conductor disposed on the contact pad, the electrical conductor comprising a laser irradiated metallic material that forms a uniform and coherent block; and

an encapsulant covering the semiconductor die and at least a portion of the electrical conductor.

2 . The semiconductor die package of claim 1 , further comprising:

a die carrier,

wherein the semiconductor die is disposed on the die carrier.

3 . The semiconductor die package of claim 1 , wherein

the electrical conductor is directly connected with the contact pad with no further layer in between.

4 . The semiconductor die package of claim 1 , wherein a barrier layer is disposed between the contact pad and the upper main face of the semiconductor die.

5 . The semiconductor die package of claim 4 , wherein the barrier layer comprises one of Ti, TiN, Ta, TaN, TiW, and W or a stack of any of Ti, TiN, Ta, TaN, TiW, and W.

6 . The semiconductor die package of claim 1 , wherein

the semiconductor die is one or more of a wide bandgap semiconductor die, a SiC die, or a GaN die.

7 . The semiconductor die package of claim 1 , wherein

the semiconductor transistor die is a power IGBT die, or a power MOSFET die, or a thyristor die.

8 . The semiconductor die package of claim 1 , wherein an upper surface of the electrical conductor is at least in part not covered by the encapsulant.

9 . The semiconductor die package of claim 8 , further comprising a heatsink applied to the upper surface of the metallic structure.

10 . The semiconductor die package of claim 1 , further comprising:

a further contact pad on the second main face of the semiconductor transistor die; and

an electrical conductor on the further contact pad and fabricated by laser-assisted structuring of metallic structures.

11 . The semiconductor die package of claim 1 , wherein a portion of the electrical conductor extends beyond a side face of the encapsulant.

12 . The semiconductor die package of claim 11 , wherein the portion of the electrical conductor that extends beyond the side face of the encapsulant is homogeneous with a portion of the electrical conductor within the encapsulant and fabricated by the same laser-assisted structuring of the metallic material.

13 . The semiconductor die package of claim 11 , wherein the portion of the electrical conductor that extends beyond the side face of the encapsulant is fabricated from a different metallic material than a portion of the electrical conductor within the encapsulant.

14 . The semiconductor die package of claim 1 , wherein the electrical conductor comprises a first portion formed directly on the contact pad, a second portion adjoining the second portion and having a clip-like structure, and a third portion forming an external contact.

15 . The semiconductor die package of claim 14 , wherein both the first portion and the second portion are fabricated by the laser-assisted structuring of the metallic material, and wherein the third portion is part of a leadframe.

16 . The semiconductor die package of claim 1 , wherein the electrical conductor comprises a first contiguous portion, a lattice portion on the first contiguous portion, and a further contiguous portion on the lattice portion, and wherein the metallic material does not fill the entire space in the lattice portion.

17 . The semiconductor die package of claim 16 , wherein the lattice portion comprises a crisscrossed pattern of strips or bars of the metallic material.

18 . The semiconductor die package of claim 1 , further comprising:

a first contact pad on a lower main face of the semiconductor transistor die; and

a backside electrical conductor disposed on the first contact pad, the backside electrical conductor comprising a laser irradiated metallic material that forms a uniform and coherent block.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 10, 2023
From: FUERGUT, EDWARD; SCHULZE, HANS-JOACHIM; ESCHER-POEPPEL, IRMGARD; NIKITIN, IVAN; GRUBER, MARTIN
To: INFINEON TECHNOLOGIES AUSTRIA AG
Reel/Frame 063275/0321 →
Priority Claims (1)
EP 20152722 · Jan 20, 2020 · regional
Continuity (2)
Division 17149891 · Jan 15, 2021
Related Publication 20230282608A1 · Sep 7, 2023
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