IP Library Granted Patent US 12,607,758
Granted Patent B2
US 12,607,758 · App. 18/027,009 · Granted Apr 21, 2026

Delta modulated baseline restoration for photon counting computed tomography

Inventor: Patrick Riehl (Wilmington, MA)
Assignee: Analog Devices, Inc.
G01T1/247A61B6/032A61B6/4241A61B6/5205G01N23/046
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Quick Facts
Patent No.
US 12,607,758
App. No.
18/027,009
Granted
Apr 21, 2026
Kind
B2
Abstract

One embodiment is a baseline restoration (“BLR”) circuit for a photo-counting computed tomography (“PCCT”) signal chain, the BLR circuit comprising a comparator for comparing a shaper voltage output from a shaper component of the PCCT signal chain with a baseline voltage, the comparator outputting a single bit indicative of whether the shaper voltage is above or below the baseline voltage; a low pass filter connected to filter a voltage signal output from the comparator; and a transconductor connected to receive a filtered voltage signal output from the low pass filter, convert the filtered voltage signal to a current signal, and feed the current signal back to an input of the PCCT signal chain.

Claims (27)

1 . A baseline restoration (“BLR”) circuit for a photon-counting computed tomography (“PCCT”) signal chain, the BLR circuit comprising:

an input comparator for comparing a shaper voltage output from a shaper component of the PCCT signal chain with a baseline voltage, the input comparator outputting a single bit indicative of whether the shaper voltage is above or below the baseline voltage; and

a low pass filter connected to filter a voltage signal output from the input comparator.

2 . The BLR circuit of claim 1 , further comprising a transconductor connected to receive a filtered voltage signal output from the low pass filter, convert the filtered voltage signal to a current signal, and feed the current signal back to an input of the PCCT signal chain.

3 . The BLR circuit of claim 1 , comprising a delta modulator circuit for providing nonlinear BLR.

4 . The BLR circuit of claim 3 , wherein the low pass filter comprises an integrator of the delta modulator circuit.

5 . The BLR circuit of claim 1 , further comprising a feedback loop that functions as a delta modulator.

6 . The BLR circuit of claim 1 , wherein the BLR circuit is clocked.

7 . The BLR circuit of claim 1 , wherein chopper stabilization is applied to null out an offset of the input comparator.

8 . The BLR circuit of claim 1 , wherein an auto-zero technique is applied to null out an offset of the input comparator.

9 . The BLR circuit of claim 1 , wherein the BLR circuit is clocked and chopper stabilization is applied to null out an offset of the input comparator.

10 . The BLR circuit of claim 1 , wherein the BLR circuit is clocked and an auto-zero technique is applied to null out an offset of the input comparator.

11 . The BLR circuit of claim 1 , wherein the low pass filter is in a non-feedback configuration.

12 . A method for implementing non-linear baseline restoration (“BLR”), the method comprising:

comparing a shaper voltage output from a shaper component of a photon-counting computed tomography (PCCT) signal chain with a baseline voltage to produce a comparator voltage indicative of whether the shaper voltage is above or below the baseline voltage at a given time;

filtering the comparator voltage; and

converting the filtered voltage signal to a current signal.

13 . The method of claim 12 , further comprising feeding the current signal back to an input of the PCCT signal chain.

14 . The method of claim 13 , wherein the comparing, filtering, converting, and feeding is performed by a delta-modulation circuit.

15 . The method of claim 12 , further comprising clocking the comparing and filtering.

16 . The method of claim 12 , further comprising applying chopper stabilization to null out an offset of an input comparator of the PCCT signal chain.

17 . The method of claim 12 , further comprising applying an auto-zero technique to null out an offset of an input comparator of the PCCT signal chain.

18 . The method of claim 12 , further comprising:

clocking the comparing and filtering; and

applying chopper stabilization to null out an offset of an input comparator of the PCCT signal chain.

19 . The method of claim 12 , wherein the filtering is performed using a low-pass filter.

20 . The method of claim 19 , further comprising applying a low-duty-cycle clock signal to the low-pass filter to increase a value of a time constant.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 8, 2023
From: RIEHL, PATRICK
To: ANALOG DEVICES, INC.
Reel/Frame 063892/0624 →
Continuity (2)
Provisional Application 63080315 · Sep 18, 2020
Related Publication 20230367025A1 · Nov 16, 2023
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