Systems and methods for direct data transmission in image processing systems
Methods and systems for efficient data movement between various components in an image processing system are described. In a first mode, a dedicated data bus is configured for direct transmission of image data between the ISP core and the video core and/or display core. Using this bus, the video core and/or display core can request data from the ISP core. The ISP core transmits data to the video core and/or display core in response to the request. If the video core is unable to process incoming data from the ISP core at the rate at which data are generated by the ISP, it can apply backpressure to the ISP core to pause transmission of data, e.g., by not consuming data transmitted from the ISP core. The data transmission is performed using a cache memory or buffer as an intermediatory, in a second mode.
1 . A system comprising:
an image signal processing (ISP) core comprising circuitry configured to receive image data;
wherein responsive to a first mode of operation, at least one of a video core and a display core is configured to receive the image data directly from the ISP core via a bus that bypasses a memory device; and
wherein responsive to a second mode of operation, at least one of the video core and the display core is configured to receive the image data from the memory device instead of via the bus.
2 . The system as recited in claim 1 , further comprising circuitry configured to select one of the first mode of operation and the second mode of operation based on one or more operating conditions comprising at least one of a latency requirement, a power-consumption state, or an availability of the at least one of the video core and the display core.
3 . The system as claimed in claim 1 , wherein responsive to the first mode of operation, at least one of the video core and the display core is configured to receive the image data as scaler output at least in part comprising scaled image data.
4 . The system as claimed in claim 1 , wherein in the first mode of operation, transmission of the image data from the ISP core to the at least one of the video core and the display core is pausable responsive to a stalling condition associated with the at least one of the video core and the display core.
5 . The system as claimed in claim 1 , wherein the ISP core is configured to transmit the image data to both the video core and the display core concurrently in the first mode of operation.
6 . The system as claimed in claim 1 , wherein the ISP core is configured to transmit the image data to at least one of the video core and the display core concurrently.
7 . The system as claimed in claim 2 , wherein the circuitry configured to select the first mode of operation or the second mode of operation comprises mode-selection logic integrated with at least one of the ISP core, the video core, or the display core, the logic being configured to perform dynamic switching between the modes during continuous image capture.
8 . A method comprising:
receiving, by circuitry of an image signal processing (ISP) core, image data;
receiving, responsive to a first mode of operation, by at least one of a video core and a display core, the received image data via a bus that bypasses a memory device; and
receiving, responsive to a second mode of operation, by at least one of the video core and the display core, the image data from the memory device instead of via the bus.
9 . The method as claimed in claim 8 , further comprising selecting one of the first mode of operation and the second mode of operation based on one or more operating conditions comprising at least one of a latency requirement, a power- consumption state, or an availability of the at least one of the video core and the display core.
10 . The method as claimed in claim 8 , further comprising receiving, by at least one of the video core and the display core in the first mode of operation, the image data as scaler output at least in part comprising scaled image data.
11 . The method as claimed in claim 8 , further comprising receiving, by at least one of the video core and the display core in the first mode of operation, the image data directly from the ISP core via the bus, responsive to a data acquisition request issued by the at least one of the video core and display core.
12 . The method as claimed in claim 11 , further comprising pausing, by the ISP core, transmission of the image data to at least one of the video core and the display core, responsive to a stalling request issued by at least one of the video core and the display core.
13 . The method as claimed in claim 8 , further comprising transmitting the image data to both the video core and the display core concurrently.
14 . The method as claimed in claim 8 , further comprising transmitting, by the ISP core, the image data to at least one of the video core and the display core in a specific order, such that the of the image data matches an order corresponding to an input of at least one of the video core and the display core.
15 . A system comprising:
an image signal processing (ISP) core comprising circuitry configured to receive image data;
at least one data bus coupled to the ISP core and to each of a video core and a display core, the at least one data bus being configured to provide a data path that bypasses a memory device; and
wherein, in a first mode of operation, the ISP core comprises circuitry configured to transmit the image data concurrently to both the video core and the display core via the at least one data bus, each of the video core and the display core being configured to process the image data independently.
16 . The system as recited in claim 15 , wherein responsive to a second mode of operation:
the ISP is configured to transmit received image data to a memory device; and
at least one of the video core and the display core is configured to retrieve the image data from the memory device instead of the at least one data bus.
17 . The system as claimed in claim 15 , wherein, in the first mode of operation, at least one of the video core and the display core is configured to receive the image data as scaler output at least in part comprising scaled image data.
18 . The system as claimed in claim 15 , wherein in the first mode of operation, at least one of the video core and the display core is configured to receive the image data directly from the ISP via the bus, responsive to a data acquisition request issued by the at least one of the video core and display core.
19 . The system as claimed in claim 18 , wherein in the first mode of operation, transmission of the image data from the ISP core to at least one of the video core and the display core is paused, responsive to a stalling request issued by at least one of the video core and the display core.
20 . The system as claimed in claim 15 , wherein the ISP core is configured to transmit the image data to at least one of the video core and the display core concurrently.