Memory device high-speed interface training
Various aspects of the present disclosure generally relate to memory device high-speed interface training. In some aspects, a memory device may perform an initial training operation for a high-speed interface of the memory device. The memory device may detect, after a completion of the initial training operation for the high-speed interface, whether an aging counter associated with the high-speed interface has expired. The memory device may initiate one or more re-training operations for the high-speed interface based at least in part on whether the aging counter has expired. In some other aspects, the memory device may detect that the memory device is in an idle state. The memory device may perform a micro-training operation for a high-speed interface of the memory device in accordance with the memory device being in the idle state. Numerous other aspects are described.
1 . A memory device, comprising:
one or more memories; and
one or more processors, coupled to the one or more memories, configured to:
perform an initial training operation for a high-speed interface;
detect, after a completion of the initial training operation for the high-speed interface, whether an aging counter associated with the high-speed interface of the memory device has expired; and
initiate one or more re-training operations for the high-speed interface based at least in part on whether the aging counter has expired.
2 . The memory device of claim 1 , wherein the one or more processors are further configured to store one or more results of the one or more re-training operations in a flash memory of the memory device.
3 . The memory device of claim 2 , wherein the one or more processors are further configured to perform a standard boot for the memory device using the one or more results of the one or more re-training operations.
4 . The memory device of claim 1 , wherein the one or more processors, to initiate the one or more re-training operations based at least in part on whether the aging counter has expired, are configured to perform a re-training operation for the high-speed interface based at least in part on detecting that the aging counter has expired.
5 . The memory device of claim 4 , wherein the one or more processors are further configured to:
detect, after a completion of the re-training operation, that the aging counter has expired; and
perform another re-training operation for the high-speed interface based at least in part on detecting that the aging counter has expired.
6 . The memory device of claim 1 , wherein the initial training operation for the high-speed interface is performed after an initial boot of the memory device.
7 . The memory device of claim 1 , wherein the one or more re-training operations are performed using a micro-controller associated with the memory device.
8 . The memory device of claim 1 , wherein the one or more re-training operations are performed using a hardware built-in self-test engine associated with the memory device.
9 . The memory device of claim 1 , wherein the one or more processors, to detect whether the aging counter has expired, are configured to check whether the aging counter has expired in accordance with an interval.
10 . The memory device of claim 1 , wherein the one or more processors, to detect whether the aging counter has expired, are configured to check whether the aging counter has expired in accordance with a standard boot for the memory device.
11 . The memory device of claim 1 , wherein the high-speed interface is a double data rate (DDR) interface.
12 . The memory device of claim 11 , wherein the initial training operation is a DDR training operation and the one or more re-training operations are one or more DDR re-training operations.
13 . The memory device of claim 1 , wherein the memory device is a very-large-scale integration memory device.
14 . The memory device of claim 1 , wherein a re-training operation of the one or more re-training operations is performed in-field over a time period that is less than two seconds.
15 . A memory device, comprising:
one or more memories; and
one or more processors, coupled to the one or more memories, configured to:
perform an initial training operation for a high-speed interface;
detect, after a completion of the initial training operation for the high-speed interface, that the memory device is in an idle state; and
perform a micro-training operation for the high-speed interface of the memory device in accordance with the memory device being in the idle state, wherein the micro-training operation includes a portion of a training operation for the high-speed interface that is less than an entirety of the training operation for the high-speed interface.
16 . The memory device of claim 15 , wherein the one or more processors, to perform the micro-training operation, are configured to perform a plurality of micro-training operations for a plurality of training categories associated with the high-speed interface.
17 . The memory device of claim 16 , wherein the plurality of training categories associated with the high-speed interface include a duty cycle calibration category, a write training category, and a read training category.
18 . The memory device of claim 15 , wherein the one or more processors, to perform the micro-training operation, are configured to perform a plurality of micro-training operations for a plurality of frequencies associated with transferring data using the high-speed interface.
19 . The memory device of claim 15 , wherein the idle state is associated with a time period that is outside of a mission mode of the memory device.
20 . The memory device of claim 15 , wherein the idle state is associated with a time period during which the memory device is not transmitting data to another device or receiving data from another device.
21 . The memory device of claim 15 , wherein the one or more processors are further configured to combine a plurality of micro-training operations performed by the memory device during one or more idle states.
22 . The memory device of claim 21 , wherein the one or more processors are further configured to save a plurality of results associated with the plurality of micro-training operations in a register associated with the high-speed interface.
23 . The memory device of claim 15 , wherein the micro-training operation is associated with a re-training of the memory device that occurs after an initial boot of the memory device.
24 . The memory device of claim 15 , wherein the high-speed interface is a double data rate (DDR) interface.
25 . The memory device of claim 15 , wherein the memory device is a very-large-scale integration memory device.
26 . The memory device of claim 15 , wherein the micro-training operation is performed using a micro-controller associated with the memory device.
27 . The memory device of claim 15 , wherein the micro-training operation is performed using a hardware built-in self-test engine associated with the memory device.
28 . A method performed by a memory device, comprising:
performing an initial training operation for a high-speed interface;
detecting, after a completion of the initial training operation for the high-speed interface, whether an aging counter associated with the high-speed interface of the memory device has expired; and
initiating one or more re-training operations for the high-speed interface based at least in part on whether the aging counter has expired.
29 . A method performed by a memory device, comprising:
performing an initial training operation for a high-speed interface;
detecting, after a completion of the initial training operation for the high-speed interface, that the memory device is in an idle state; and
performing a micro-training operation for the high-speed interface of the memory device in accordance with the memory device being in the idle state, wherein the micro-training operation includes a portion of a training operation for the high-speed interface that is less than an entirety of the training operation for the high-speed interface.