Address mapping for improved reliability
The internal row addressing of each DRAM on a module is mapped such that row hammer affects different neighboring row addresses in each DRAM. Because the external row address to internal row address mapping scheme ensures that each set of neighboring rows for a given externally addressed row is different for each DRAM on the module, row hammering of a given externally addressed row spreads the row hammering errors across different externally addressed rows on each DRAM. This has the effect of confining the row hammer errors for each row that is hammered to a single DRAM per externally addressed neighboring row. By confining the row hammer errors to a single DRAM, the row hammer errors are correctible using a single device data correct (SDDC) scheme.
1 . A memory module, comprising:
a command/address interface to receive a first row address;
a first dynamic random access memory (DRAM) device including a first memory array and first neighbor-refresh control circuitry, the first DRAM device to receive the first row address and to, based on the first row address, access a first row in the first memory array having a first internal row address, the first row to be physically next to a first neighboring row having a first internal neighboring row address, the first DRAM device to also, based on receiving a neighbor refresh command associated with the first row address, refresh the first neighboring row; and
a second DRAM device including a second memory array and second neighbor-refresh control circuitry, the second DRAM device to receive the first row address and to, based on the first row address, access a second row in the second memory array having a second internal row address, the second row to be physically next to a second neighboring row having a second internal neighboring row address, the second DRAM device to also, based on receiving the neighbor refresh command associated with the first row address, refresh the second neighboring row, wherein a first address that the first DRAM receives that maps to the first internal neighboring row address and a second address that the second DRAM receives that maps to the second internal neighboring row address are to be not equal.
2 . The memory module of claim 1 , wherein the first DRAM device comprises first row address remapping circuitry to map the first row address to the first internal row address and the second DRAM device comprises second address remapping circuitry to map the first row address to the second internal row address.
3 . The memory module of claim 2 , wherein the first address remapping permutes the first row address using a first permutation function when mapping the first row address to the first internal row address and the second address remapping circuitry permutes the first row address using a second permutation function when mapping the first row address to the second internal row address, wherein the first permutation function and the second permutation function are not equivalent.
4 . The memory module of claim 2 , wherein the first row address remapping circuitry circularly shifts the first row address by a first number of bits when mapping the first row address to the first internal row address and the second row address remapping circuitry circularly shifts the first row address by a second number of bits when mapping the first row address to the second internal row address, wherein the first number of bits and the second number of bits are not functionally equivalent.
5 . The memory module of claim 2 , wherein the first row address remapping circuitry comprises first linear feedback shift register (LFSR) circuitry and the second row address remapping circuitry comprises second LFSR circuitry, the first LFSR circuitry and the second LFSR circuitry configured to produce different outputs when provided a same input value.
6 . The memory module of claim 3 , wherein the first DRAM device and the second DRAM device, when respectively placed in a first mode, are to respectively use the first permutation function and when respectively placed in a second mode, are to respectively use the second permutation function.
7 . The memory module of claim 3 , further comprising a register that determines a permutation function to be used.
8 . A dynamic random access memory (DRAM) device, comprising:
a memory array having a plurality of rows accessed according to a plurality of internal row addresses;
a command/address interface to receive a plurality of external row addresses; and
externally configurable row address mapping circuitry to, based on a mapping mode indicator, select a one of a plurality of mapping modes, each of the plurality of mapping modes to provide unique, among the plurality of mapping modes, translations of the plurality of external row addresses to corresponding ones of the plurality of internal row addresses; and
neighbor-refresh control circuitry to, based on the selected one of the plurality of mapping modes, provide translations of a plurality of external neighbor row refresh addresses to corresponding ones of the plurality of internal row addresses to be refreshed.
9 . The DRAM device of claim 8 , wherein each of the plurality of rows has a corresponding at least one neighboring row that is physically next to each respective one of the plurality of rows, and each of the plurality of mapping modes provide unique, among the plurality of mapping modes, translations of the plurality of external row addresses to corresponding ones of the plurality of internal row addresses of the at least one neighboring row.
10 . The DRAM device of claim 8 , wherein the plurality of mapping modes provide unique, among the plurality of mapping modes, permutation functions to translate the plurality of external row addresses to corresponding ones of the plurality of internal row addresses.
11 . The DRAM device of claim 8 , wherein the plurality of mapping modes provide unique, among the plurality of mapping modes, circular shift functions to translate the plurality of external row addresses to corresponding ones of the plurality of internal row addresses.
12 . The DRAM device of claim 8 , wherein the plurality of mapping modes use unique, among the plurality of mapping modes, linear feedback shift register functions when translating the plurality of external row addresses to corresponding ones of the plurality of internal row addresses.
13 . The DRAM device of claim 8 , wherein the command/address interface is to receive a command that determines the mapping mode indicator.
14 . The DRAM device of claim 8 , wherein the mapping mode indicator is nonvolatile.
15 . A method of operating a memory module, comprising:
receiving, via a command/address interface, a first row address;
receiving, by a first dynamic random access memory (DRAM) device on the memory module that includes a first memory array, the first row address;
based on the first row address, accessing a first row in the first memory array that has a first internal row address, the first row to be physically next to a first neighboring row having a first internal neighboring row address;
receiving, by the first DRAM device and the second DRAM device, the first row address in association with a first neighbor refresh command;
based on the first neighbor refresh command and the first row address, refreshing, by the first DRAM device, the first neighboring row;
receiving, by a second DRAM device on the memory module that includes a second memory array, the first row address; and
based on the first row address, accessing a second row in the second memory array that has a second internal row address, the second row to be physically next to a second neighboring row having a second internal neighboring row address where a first external row address received via the command/address interface that maps to the first internal neighboring row address and a second external row address received via the command/address interface that maps to the second internal neighboring row address are not equal; and
based on the first neighbor refresh command and the first row address, refreshing, by the second DRAM device, the second neighboring row.
16 . The method of claim 15 , further comprises:
mapping, by first DRAM device, the first row address to the first internal row address; and
mapping, by the second DRAM device the first row address to the second internal row address.
17 . The method of claim 16 , wherein the mapping, by the first DRAM device, of the first row address to the first internal row address, permutes the first row address using a first permutation function, and the mapping, by the second DRAM device, of the second row address to the second internal row address, permutes the first row address using a second permutation function.
18 . The method of claim 16 , wherein the mapping, by the first DRAM device, of the first row address to the first internal row address circularly shifts the first row address by a first number of bits, and the mapping, by the second DRAM device, of the second row address to the second internal row address circularly shifts the first row address by a second number of bits where the first number of bits and the second number of bits produce different outputs.
19 . The method of claim 16 , wherein the mapping, by the first DRAM device, of the first row address to the first internal row address uses a first linear feedback shift register (LFSR) function, and the mapping, by the second DRAM device, of the second row address to the second internal row address uses a second LFSR function, where the first LFSR function and the second LFSR function are configured to produce different outputs when provided a same input value.
20 . The method of claim 17 , wherein the first DRAM device and the second DRAM device, when respectively placed in a first mode, respectively use the first permutation function and when respectively placed in a second mode, respectively use the second permutation function.