Multi-layered source and drain contacts for a thin film transistor (TFT) structure
Techniques for forming thin film transistors (TFTs) having multilayer contact structures. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, a semiconductor region on the gate dielectric, and a conductive contact that contacts at least a portion of the semiconductor region. In some other cases, the conductive contact comprises a multilayer structure having at least a first material layer on the at least a portion of the semiconductor region, at least a second material layer on the first material layer, and a conductive fill material over the first and second material layers. In some other cases, the conductive contact comprises a multilayer structure having (1) a graded material layer on the at least a portion of the semiconductor region and (2) a conductive fill material over the graded material layer, wherein the graded material layer comprises a concentration gradient of a given element.
1 . An integrated circuit, comprising:
a gate electrode,
a gate dielectric on the gate electrode,
a semiconductor region on the gate dielectric, and
a conductive contact that contacts at least a portion of the semiconductor region,
wherein the conductive contact comprises a multilayer structure having at least a first material layer on the at least a portion of the semiconductor region, at least a second material layer on the first material layer, and a conductive fill material over the first and second material layers, wherein the semiconductor region and the first material layer each includes a plurality of same elements, and wherein one of the elements has a higher concentration in the first material layer compared to the semiconductor region.
2 . The integrated circuit of claim 1 , wherein the conductive contact is a first conductive contact of a thin film transistor (TFT) structure and the TFT structure comprises a second conductive contact that contacts at least a portion of the semiconductor region, wherein the second conductive contact also comprises a multilayer structure.
3 . The integrated circuit of claim 1 , wherein each of the gate electrode, the gate dielectric, the semiconductor region on the gate dielectric, and the conductive contact is part of a transistor structure that is part of an array of transistor structures within an interconnect structure.
4 . A printed circuit board comprising the integrated circuit of claim 1 .
5 . The integrated circuit of claim 1 , wherein the first material layer and the second material layer each has a thickness between 0.5 nm and 10 nm.
6 . The integrated circuit of claim 1 , wherein the semiconductor region comprises oxygen, indium, gallium, and zinc.
7 . The integrated circuit of claim 6 , wherein the first material layer comprises oxygen, indium, gallium, and zinc, with a higher concentration of indium or gallium compared to the semiconductor region.
8 . The integrated circuit of claim 7 , wherein the second material layer comprises oxygen, indium, gallium, and zinc, with a higher concentration of indium or gallium compared to the first material layer.
9 . An integrated circuit, comprising:
a plurality of semiconductor devices;
an interconnect region above the plurality of semiconductor devices, the interconnect region comprising a plurality of stacked interconnect layers; and
a thin film transistor (TFT) structure across one or more interconnect layers of the plurality of stacked interconnect layers, the TFT structure comprising
a gate electrode,
a gate dielectric on the gate electrode,
a semiconductor region on the gate dielectric, and
a conductive contact that contacts at least a portion of the semiconductor region,
wherein the conductive contact comprises a multilayer structure having at least a first material layer on the at least a portion of the semiconductor region, at least a second material layer on the first material layer, and a conductive fill material over the first and second material layers.
10 . The integrated circuit of claim 9 , wherein the semiconductor region and the first material layer each include a plurality of same elements, wherein one of the elements has a higher concentration in the first material layer compared to the semiconductor region.
11 . The integrated circuit of claim 9 , wherein the TFT structure is one TFT structure of an array of TFT structures within the interconnect region.
12 . A printed circuit board comprising the integrated circuit of claim 9 .
13 . The integrated circuit of claim 9 , wherein the semiconductor region comprises oxygen, indium, gallium, and zinc.
14 . The integrated circuit of claim 13 , wherein the first material layer comprises oxygen, indium, gallium, and zinc, with a higher concentration of indium or gallium compared to the semiconductor region.
15 . The integrated circuit of claim 14 , wherein the second material layer comprises oxygen, indium, gallium, and zinc, with a higher concentration of indium or gallium compared to the first material layer.
16 . An integrated circuit, comprising:
a gate electrode,
a gate dielectric on the gate electrode,
a semiconductor region on the gate dielectric, and
a conductive contact that contacts at least a portion of the semiconductor region,
wherein the conductive contact comprises (1) a graded material layer on the at least a portion of the semiconductor region and (2) a conductive fill material over the graded material layer, wherein the graded material layer comprises a concentration gradient of a given element having a first concentration at an interface with the conductive fill and a second concentration at an interface with the semiconductor region, the first concentration being different than the second concentration.
17 . The integrated circuit of claim 16 , wherein the semiconductor region and the graded material layer each include a plurality of same elements.
18 . A printed circuit board comprising the integrated circuit of claim 16 .
19 . The integrated circuit of claim 16 , wherein the semiconductor region comprises oxygen, indium, gallium, and zinc.
20 . The integrated circuit of claim 19 , wherein the graded material layer comprises oxygen, indium, gallium, and zinc, with indium or gallium being the given element.