Integrated radar signal processing circuit
A circuit includes a signal processing unit to generate a radar map represented by an array with a first index and a second index, and a peak detection unit to identify potential targets in the radar map. Within the peak detection unit, a first peak detection sub-unit scans the radar map along the first index and stores a first detection bitmap that identifies peaks as a function of the first index, and a second peak detection sub-unit scans the radar map along the second index and outputs a second detection bitmap that identifies peaks as a function of the second index. The first detection bitmap and the second detection bitmap identify the peaks using a single bit. A hardware accelerator processes individual bits of the first detection bitmap and of the second detection bitmap.
1 . An integrated radar signal processing circuit, comprising:
a signal processing unit configured to generate a radar map which is represented by an array with a first index and a second index;
a peak detection unit, configured to identify potential targets in the radar map, wherein the peak detection unit comprises:
a first peak detection sub-unit configured to scan the radar map along the first index and store in a radar data memory a first detection bitmap that identifies peaks as a function of the first index, and
a second peak detection sub-unit configured to scan the radar map along the second index and output into the radar data memory a second detection bitmap that identifies peaks as a function of the second index,
wherein the first detection bitmap and the second detection bitmap identify each of the peaks using a single bit value; and
a hardware accelerator connected to the radar data memory, wherein the hardware accelerator is configured to, for each bit of the first detection bitmap and the second detection bitmap,
increment a counter;
in response to the bit indicating a peak, determine a corresponding index value pair based on the counter value; and
add the determined index value pair to a list of index value pairs corresponding to respective peaks identified in the bitmap.
2 . The integrated radar signal processing circuit according to claim 1 , wherein the hardware accelerator is configured to transpose the first detection bitmap and/or the second detection bitmap.
3 . The integrated radar signal processing circuit according to claim 1 , wherein the radar data memory is an internal memory of the integrated radar signal processing circuit.
4 . The integrated radar signal processing circuit according to claim 1 , wherein the hardware accelerator comprises:
a storage element used to store the bitmap; and
a comparator logic used to compare the bit with a single bit value that indicates no peak and to output a corresponding event in response to the bit comprising the single bit value indicating a peak.
5 . The integrated radar signal processing circuit according to claim 1 , wherein the hardware accelerator is configured to output a first value given by higher-order bits of the counter and a second value given by lower-order bits of the counter as the index value pair of a peak.
6 . An integrated radar signal processing circuit, comprising:
a signal processing unit configured to generate a radar map represented by an array with a first index and a second index;
a peak detection unit, configured to identify potential targets in the radar map, wherein the peak detection unit comprises:
a first peak detection sub-unit configured to scan the radar map along the first index and store in a radar data memory a first detection bitmap that identifies peaks as a function of the first index, and
a second peak detection sub-unit configured to scan the radar map along the second index and output into the radar data memory a second detection bitmap that identifies peaks as a function of the second index,
wherein the first detection bitmap and the second detection bitmap identify each of the peaks using a single bit; and
a hardware accelerator connected to the radar data memory, wherein the hardware accelerator is configured to combine individual bits of the first detection bitmap and the second detection bitmap to generate a combined detection bitmap.
7 . The integrated radar signal processing circuit according to claim 6 , wherein the combining of the first detection bitmap with the second detection bitmap comprises multiplication of each bit of the first detection bitmap with a respective bit of the second detection bitmap, so that the combined detection bitmap identifies peaks that are identified by both the first detection bitmap and the second detection bitmap.
8 . The integrated radar signal processing circuit according to claim 6 , wherein the hardware accelerator is configured to transpose the first detection bitmap for the combination, so that during the combination each bit of the first detection bitmap is combined with a bit of the second detection bitmap that has the value of the first index of the bit of the first detection bitmap as the value of the second index, and has the value of the second index of the bit of the first detection bitmap as the value of the first index.
9 . The integrated radar signal processing circuit according to claim 6 , wherein the hardware accelerator is configured to determine a value of the first index and a value of the second index of peaks identified by the combined detection bitmap.
10 . The integrated radar signal processing circuit according to claim 9 , wherein the hardware accelerator is configured to generate and output a list of values of the first index and of associated values of the second index of the peaks identified by the combined detection bitmap.
11 . The integrated radar signal processing circuit according to claim 6 , wherein the hardware accelerator comprises:
a storage element used to store the combined detection bitmap;
a hardware counter for counting bits; and
a comparator logic used to receive the bit identified by the hardware counter and to output a corresponding event if the bit identifies a peak.
12 . The integrated radar signal processing circuit according to claim 11 , wherein the comparator logic is configured to output the event to a list generation circuit of the hardware accelerator configured to output a first value given by higher-order bits of the hardware counter and a second value given by lower-order bits of the hardware counter, as an index-value pair of a peak.
13 . The integrated radar signal processing circuit according to claim 6 , wherein the hardware accelerator has an internal bitmap memory configured to store the first detection bitmap, the second detection bitmap, or the combination of the first detection bitmap with the second detection bitmap and is configured to output the stored bitmap as a bit stream to a processing logic circuit of the hardware accelerator configured to process the bits of the bit stream individually.
14 . The integrated radar signal processing circuit according to claim 13 , wherein the processing logic circuit is configured to compare each bit of the bit stream with a fixed value or to combine each bit with a respective bit of a bit stream of another bitmap.
15 . The integrated radar signal processing circuit according to claim 13 , wherein the hardware accelerator is configured to read the first detection bitmap, the second detection bitmap and/or the combination of the first detection bitmap with the second detection bitmap into the internal bitmap memory completely and then subject them to bitwise processing.
16 . The integrated radar signal processing circuit according to claim 13 , wherein the hardware accelerator has a read interface configured to read, in parallel, rows or columns of the first detection bitmap, the second detection bitmap and/or the combination of the first detection bitmap with the second detection bitmap.
17 . The integrated radar signal processing circuit according to claim 16 , wherein the first index is a distance index and the second index is a Doppler index, wherein the first index is a distance index and the second index is a direction index, or wherein the first index is a speed index and the second index is a direction index.
18 . A method, comprising:
generating a radar map which is represented by an array with a first index and a second index;
identifying potential targets in the radar map by
scanning the radar map along the first index and storing in a radar data memory a first detection bitmap that identifies peaks as a function of the first index, and
scanning the radar map along the second index and outputting into the radar data memory a second detection bitmap that identifies peaks as a function of the second index,
wherein the first detection bitmap and the second detection bitmap identify each of the peaks using a single bit value; and
for each bit of the first detection bitmap and the second detection bitmap,
incrementing a counter;
in response to the bit indicating a peak, determining a corresponding index value pair based on the counter value; and
adding the determined index value pair to a list of index value pairs corresponding to respective peaks identified in the bitmap.
19 . The method of claim 18 , comprising outputting a corresponding event in response to the bit indicating a peak.
20 . The method of claim 18 , comprising outputting a first value given by higher-order bits of the counter and a second value given by lower-order bits of the counter as the index value pair of a peak.