Low-profile power supply regulator utilizing flipped voltage follower
A method for operating a voltage regulator is disclosed. The voltage regulator includes a first transistor and a second transistor, wherein a source of the first transistor is coupled to a supply rail, a drain of the first transistor is coupled to an output of the voltage regulator, a source of the second transistor is coupled to the output of the voltage regulator, and a drain of the second transistor is coupled to a gate of the first transistor via a feedback path. The method includes generating a current, passing the current through a resistor and a third transistor to generate a reference voltage, adjusting a resistance of the third transistor based on an output voltage at the output of the voltage regulator, and inputting the reference voltage to a gate of the second transistor.
1 . A voltage regulator, comprising:
a first transistor, wherein a source of the first transistor is coupled to a supply rail, and a drain of the first transistor is coupled to an output of the voltage regulator;
a second transistor, wherein a source of the second transistor is coupled to the output of the voltage regulator, and a drain of the second transistor is coupled to a gate of the first transistor via a feedback path;
a first current source coupled to the drain of the second transistor;
a second current source;
a third transistor, wherein a gate of the third transistor is coupled to the output of the voltage regulator, and a source of the third transistor is coupled to a ground; and
a resistor coupled between a drain of the third transistor and the second current source, wherein a gate of the second transistor is coupled between the resistor and the second current source.
2 . The voltage regulator of claim 1 , further comprising a low pass filter coupled between the resistor and the gate of the second transistor.
3 . The voltage regulator of claim 2 , wherein the low pass filter comprises a resistor-capacitor (RC) low pass filter.
4 . The voltage regulator of claim 1 , wherein the second current source comprises:
a fourth transistor, wherein a drain of the fourth transistor is coupled to the resistor;
a fifth transistor, wherein a drain of the fifth transistor is coupled to a source of the fourth transistor, and a source of the fifth transistor is coupled to the supply rail;
a gate bias circuit configured to bias a gate of the fourth transistor; and
a controller coupled to the gate of the fourth transistor, wherein the controller is configured to turn on the fourth transistor when the second current source is enabled.
5 . The voltage regulator of claim 4 , wherein the second transistor comprises a first p-type field effect transistor, and the fifth transistor comprises a second p-type field effect transistor.
6 . The voltage regulator of claim 4 , wherein the controller is configured to turn off the fourth transistor when the second current source is disabled.
7 . The voltage regulator of claim 4 , wherein the controller is configured to couple the gate of the fourth transistor to the ground to turn on the fourth transistor.
8 . The voltage regulator of claim 4 , wherein the gate bias circuit comprises a current mirror configured to bias the gate of the fourth transistor based on a reference current.
9 . The voltage regulator of claim 1 , wherein the first transistor comprises a first p-type field effect transistor, the second transistor comprises a second p-type field effect transistor, and the third transistor comprises an n-type field effect transistor.
10 . The voltage regulator of claim 1 , wherein the output of the voltage regulator is coupled to one or more clock buffers.
11 . A method for operating a voltage regulator including a first transistor and a second transistor, wherein a source of the first transistor is coupled to a supply rail, a drain of the first transistor is coupled to an output of the voltage regulator, a source of the second transistor is coupled to the output of the voltage regulator, and a drain of the second transistor is coupled to a gate of the first transistor via a feedback path, the method comprising:
generating a current;
passing the current through a resistor and a third transistor to generate a reference voltage;
adjusting a resistance of the third transistor based on an output voltage at the output of the voltage regulator; and
inputting the reference voltage to a gate of the second transistor.
12 . The method of claim 11 , wherein adjusting the resistance of the third transistor based on the output voltage comprises:
operating the third transistor in a triode region; and
coupling the output of the voltage regulator to a gate of the third transistor.
13 . The method of claim 11 , wherein generating the current comprises generating the current using a fourth transistor, and the method further comprises providing a source degeneration resistance at a source of the fourth transistor.
14 . The method of claim 13 , wherein providing the source degeneration resistance comprises providing the source degeneration resistance using a fifth transistor, wherein a threshold voltage of the fifth transistor tracks a threshold voltage of the second transistor.
15 . The method of claim 14 , further comprising operating the fifth transistor in a triode region.
16 . The method of claim 13 , wherein generating the current further comprises biasing a gate of the fourth transistor based on a reference current using a current mirror.
17 . The method of claim 11 , further comprising filtering the reference voltage using a low pass filter.