Memory controller fractonal bandwidth adjustment for critical and non- critical components
A memory controller is provided and configured to control access to a memory with a memory access bandwidth by a plurality of processing components of a data processing system. The memory controller comprises a control unit configured to allocate a respective fraction of the memory access bandwidth to each of the plurality of processing components for accessing the memory by a plurality of memory access operations. Moreover, the memory controller comprises a monitoring unit configured to obtain timing information about a duration of a respective memory access operation by each of the plurality of processing components via a bus of the data processing system. The control unit is further configured to adjust, for one or more of the plurality of processing components, the respective fraction of the memory access bandwidth based on the timing information obtained by the monitoring unit.
1 . A memory controller for controlling access to a memory with a memory access bandwidth by a plurality of processing components of a data processing system, wherein the memory controller comprises:
a controller configured to allocate a respective fraction of the memory access bandwidth to each of the plurality of processing components for accessing the memory by a plurality of memory access operations;
a monitor device configured to obtain timing information about a duration of a respective memory access operation by each of the plurality of processing components via a bus of the data processing system;
wherein the controller is further configured to adjust, for one or more of the plurality of processing components, the respective fraction of the memory access bandwidth based on the timing information obtained by the monitor device;
wherein based on a memory access operation for a critical processing component having exceeded a corresponding timing requirement, the controller is further configured to:
register one or more current bandwidth values of corresponding one or more non-critical processing components associated with most recent transactions, as corresponding one or more maximum bandwidth values;
reduce, by a configurable amount, the one or more current bandwidth values of the corresponding one or more non-critical processing components associated with the most recent transactions; and
wherein each identity of the one or more non-critical processing components associated with the most recent transactions is recorded in a list stored in a first-in-first-out (FIFO) buffer, and the controller is configured to retrieve the list from the FIFO buffer and determine the configurable amount based on the list and a respective current bandwidth setting.
2 . The memory controller of claim 1 , wherein the monitor device is further configured to determine, for a respective memory access operation, the processing component performing the respective memory access operation.
3 . The memory controller of claim 1 , wherein the plurality of processing components comprises:
one or more critical processing components and one or more non-critical processing components, and
wherein the controller is further configured to adjust, for the one or more non-critical processing components, the respective fraction of the memory access bandwidth based on the timing information obtained by the monitor device for the one or more critical processing components.
4 . The memory controller of claim 3 , wherein the controller is configured to increase, for the one or more non-critical processing components, the respective fraction of the memory access bandwidth, based on the timing information indicating that the duration of a memory access operation by the one or more critical processing components is smaller than a respective threshold value.
5 . The memory controller of claim 4 , wherein the controller is configured to increase, for the one or more non-critical processing components, the respective fraction of the memory access bandwidth to a value smaller than or equal to a maximum threshold value.
6 . The memory controller of claim 3 , wherein the controller is configured to decrease, for the one or more non-critical processing components, the respective fraction of the memory access bandwidth, based on the timing information indicating that the duration of a memory access operation by the one or more critical processing components is longer than a respective threshold value.
7 . The memory controller of claim 6 , wherein the controller is configured to decrease the fraction of the memory access bandwidth for the non-critical processing component with the most recent memory access operation.
8 . The memory controller of claim 6 , wherein the memory controller is configured to operate in a calibration mode, and
wherein during the calibration mode, the controller is configured to calibrate the respective threshold value for the one or more critical processing components.
9 . The memory controller of claim 8 , wherein during the calibration mode, the controller is configured to calibrate the respective threshold value for the one or more critical processing components based on a fraction of a respective measured memory access duration for the respective critical processing component.
10 . The memory controller of claim 5 , wherein the controller is further configured to determine the one or more critical processing components and the one or more non-critical processing components of the plurality of processing components; and/or to obtain information indicative of the one or more critical processing components and the one or more non-critical processing components of the plurality of processing components.
11 . The memory controller of claim 1 , wherein the controller is further configured to determine, based on the timing information and/or memory access address information obtained by the monitor device a first or a second memory access pattern of the plurality of processing components, and
wherein, in response to the first memory access pattern being determined, the controller is configured to assign a respective first fraction of the memory access bandwidth to each of the plurality of processing components, and
wherein in response to the second memory access pattern being determined, the controller is configured to assign a respective second fraction of the memory access bandwidth to each of the plurality of processing components.
12 . The memory controller of claim 11 , wherein the first memory access pattern is a sequential memory access pattern, and the second memory access pattern is a random memory access pattern.
13 . A data processing system, comprising:
a memory;
a plurality of processing components configured to access the memory by one or more memory access operations; and
a memory controller for controlling access to a memory with a memory access bandwidth by a plurality of processing components of a data processing system, wherein the memory controller comprises:
a controller configured to allocate a respective fraction of the memory access bandwidth to each of the plurality of processing components for accessing the memory by a plurality of memory access operations;
a monitor device configured to obtain timing information about a duration of a respective memory access operation by each of the plurality of processing components via a bus of the data processing system;
wherein the controller is further configured to adjust, for one or more of the plurality of processing components, the respective fraction of the memory access bandwidth based on the timing information obtained by the monitor device;
wherein based on a memory access operation for a critical processing component having exceeded a corresponding timing requirement, the controller is further configured to:
register one or more current bandwidth values of corresponding one or more non-critical processing components associated with most recent transactions, as corresponding one or more maximum bandwidth values;
reduce, by a configurable amount, the one or more current bandwidth values of the corresponding one or more non-critical processing components associated with the most recent transactions; and
wherein each identity of the one or more non-critical processing components associated with the most recent transactions is recorded in a list stored in a first-in-first-out (FIFO) buffer, and the controller is configured to retrieve the list from the FIFO buffer and determine the configurable amount based on the list and a respective current bandwidth setting.
14 . A method for controlling access of a memory with a memory access bandwidth by a plurality of processing components of a data processing system, wherein the method which is applied to a memory controller comprises:
allocating a respective fraction of the memory access bandwidth to each of the plurality of processing components for accessing the memory by a plurality of memory access operations;
obtaining timing information about a duration of a respective memory access operation by each of the plurality of processing components via a bus of the data processing system; and
adjusting for one or more of the plurality of processing components the respective fraction of the memory access bandwidth based on the obtained timing information;
wherein based on a memory access operation for a critical processing component having exceeded a corresponding timing requirement, the method further comprises:
registering one or more current bandwidth values of corresponding one or more non-critical processing components associated with most recent transactions, as corresponding one or more maximum bandwidth values;
reducing, by a configurable amount, the one or more current bandwidth values of the corresponding one or more non-critical processing components associated with the most recent transactions; and
wherein each identity of the one or more non-critical processing components associated with the most recent transactions is recorded in a list stored in a first-in-first-out (FIFO) buffer, and the controller is configured to retrieve the list from the FIFO buffer and determine the configurable amount based on the list and a respective current bandwidth setting.
15 . A non-transitory computer-readable storage medium for storing program code which, upon execution by a computer or a processor, causes the computer or the processor to perform the method of claim 14 .
16 . The data processing system of claim 13 , wherein the monitor device is further configured to determine, for a respective memory access operation, the processing component performing the respective memory access operation.
17 . The data processing system of claim 13 , wherein the plurality of processing components comprises:
one or more critical processing components and one or more non-critical processing components, and
wherein the controller is further configured to adjust, for the one or more non-critical processing components, the respective fraction of the memory access bandwidth based on the timing information obtained by the monitor device for the one or more critical processing components.
18 . The data processing system of claim 13 , wherein the controller is configured to increase, for the one or more non-critical processing components, the respective fraction of the memory access bandwidth, based on the timing information indicating that the duration of a memory access operation by the one or more critical processing components is smaller than a respective threshold value.
19 . The method of claim 14 , further comprising:
determining, for a respective memory access operation, the processing component performing the respective memory access operation.
20 . The method of claim 14 , wherein the plurality of processing components comprises:
one or more critical processing components and one or more non-critical processing components, and
wherein the method further comprises: adjusting, for the one or more non-critical processing components, the respective fraction of the memory access bandwidth based on the obtained timing information for the one or more critical processing components.