System, apparatus and method for throttling fusion of micro-operations in a processor
In one embodiment, an apparatus includes: a plurality of execution circuits to execute and instruct micro-operations (μops), where a subset of the plurality of execution circuits are capable of execution of a fused μop; a fusion circuit coupled to at least the subset of the plurality of execution circuits, wherein the fusion circuit is to fuse at least some pairs of producer-consumer μops into fused μops; and a fusion throttle circuit coupled to the fusion circuit, wherein the fusion throttle circuit is to prevent a first μop from being fused with another μop based at least in part on historical information associated with the first μop. Other embodiments are described and claimed.
1 . An apparatus comprising:
a plurality of execution circuits to execute micro-operations (μops), wherein a subset of the plurality of execution circuits are capable of execution of a fused μop;
a fusion circuit coupled to at least the subset of the plurality of execution circuits, wherein the fusion circuit is to fuse one or more pairs of producer-consumer μops into fused μops; and
a fusion throttle circuit coupled to the fusion circuit, the fusion throttle circuit comprising a memory to store a plurality of entries, each of the plurality of entries to store an identifier of a fused μop and associated historical information comprising a confidence value, wherein the fusion throttle circuit is to prevent a first μop from being fused with another μop based at least in part on historical information associated with the first μop and, wherein the fusion throttle circuit is to update the confidence value of a first entry in the memory associated with a first fused μop when a number of attempts to dispatch the first fused μop exceeds a threshold.
2 . The apparatus of claim 1 , wherein the fusion throttle circuit is to prevent the fusion of the first pop with the another μop based on a comparison between the confidence value of an entry in the memory associated with the first μop and a second threshold.
3 . The apparatus of claim 1 , wherein the fusion throttle circuit is to remove an entry associated with a fused uop from the memory when the fused μop is dispatched in a cycle in which at least one of the subset of the plurality of execution circuits is free.
4 . The apparatus of claim 1 , further comprising an allocation circuit comprising the fusion circuit, wherein the allocation circuit is to consult the fusion throttle circuit and fuse a second μop with a third μop to form a second fused μop based at least in part on historical information associated with the second μop.
5 . The apparatus of claim 4 , further comprising a reservation station coupled to the allocation circuit, wherein the allocation circuit is to provide the second fused μop to the reservation station.
6 . The apparatus of claim 5 , further comprising a scheduler circuit coupled to the reservation station, the scheduler circuit to schedule in a first cycle the second fused μop to one of the subset of the plurality of execution circuits.
7 . The apparatus of claim 6 , wherein the scheduler circuit is to schedule in the first cycle the third μop to another one of the plurality of execution circuits, the third μop a producer μop and the second μop a consumer uop.
8 . The apparatus of claim 1 , wherein at least one of the subset of the plurality of execution circuits is to receive more than two source operands and perform on an operation on the more than two source operands in a single cycle.
9 . A processor comprising:
an allocation circuit to allocate micro-operations (μops) to execution ports that couple to execution units;
a scheduler circuit coupled to the allocation circuit, wherein the scheduler circuit is to schedule the μops to allocated execution ports;
the execution units coupled to the scheduler circuit to execute scheduled μops, wherein a subset of the execution units are capable of execution of a fused μop; and
a memory to store a plurality of entries, each of the plurality of entries to store an identifier of a fused uop and associated historical information comprising a confidence value,
wherein the allocation circuit is to fuse at least one pair of producer-consumer μops into a fused μop when the at least one pair is to be scheduled in a same cycle and to not fuse a first consumer μop with a first producer μop based at least in part on historical information associated with the first consumer μop, and wherein the allocation circuit is to prevent fusion of the first consumer μop with the first producer μop based on a comparison between the confidence value of an entry in the memory associated with the first consumer μop and a threshold.
10 . The processor of claim 9 , wherein the scheduler circuit is to update the confidence value of a first entry in the memory associated with a first fused μop when a number of attempts to schedule the first fused μop exceeds a second threshold.
11 . The processor of claim 9 , wherein the subset of the execution units are to receive M+1 source operands and others of the execution units are to receive M source operands.