Hard partitioning via intra-SOC composition
Described herein is a partitional graphics processor having multiple hard partitions with separate software execution and fault domains. One embodiment provides a graphics processor comprising a system interface and a plurality of graphics processing resources coupled with the system interface. The plurality of graphics processing resources is configurable to be partitioned into a plurality of isolated device partitions, each isolated device partition configured for fault isolation and independent concurrent execution of workloads associated with a plurality of clients, and the system interface is configured to present each of the plurality of isolated device partitions as a virtual function.
1 . A graphics processing unit comprising:
a system interface; and
graphics processing circuitry coupled with the system interface, wherein the graphics processing circuitry is configurable to be partitioned into a plurality of isolated device partitions, each of the plurality of isolated device partitions having an independent reset and power management domain configured for fault isolation and independent concurrent execution of a workload of a plurality of workloads associated with a plurality of clients, the system interface is configured to present each of the plurality of isolated device partitions as a virtual function, wherein the graphics processing circuitry is configured to enable independent performance profiling for each of the plurality of isolated device partitions, and profiling data for an isolated device partition is accessible via a virtual function unit associated with the isolated device partition.
2 . The graphics processing unit as in claim 1 , wherein each isolated device partition includes an independent media engine.
3 . The graphics processing unit as in claim 1 , wherein the graphics processing circuitry includes a plurality of graphics processor cores or a plurality of graphics processor core clusters.
4 . The graphics processing unit as in claim 1 , wherein the system interface is configured to present a first virtual function associated with a first isolated device partition and a second virtual function associated with a second isolated device partition.
5 . The graphics processing unit as in claim 4 , wherein the first isolated device partition includes a first microcontroller that includes a first scheduler to schedule workloads for execution by the first isolated device partition and the second isolated device partition includes a second microcontroller that includes a second scheduler to schedule workloads for execution by the second isolated device partition.
6 . The graphics processing unit as in claim 5 , additionally including a plurality of hardware tiles, each hardware tile including a portion of the graphics processing circuitry, wherein the plurality of hardware tiles includes a first hardware tile associated with a first virtual function and a second hardware tile associated with a second virtual function.
7 . The graphics processing unit as in claim 5 , additionally including a plurality of chiplets, each chiplet an at least partially packaged integrated circuit including a portion of the graphics processing circuitry, wherein the plurality of chiplets includes a first chiplet associated with a first virtual function and a second chiplet associated with a second virtual function.
8 . The graphics processing unit as in claim 1 , wherein the graphics processing circuitry is configured to is accessible via a virtual function unit associated with the isolated device partition compose a composite device partition via selection, from collections of fixed function and programmable logic within the graphics processing unit, of one or more cache partitions, memory partitions, fixed function units, and compute partitions for each device partition.
9 . A data processing system comprising:
a memory device to store instructions; and
a graphics processing unit including graphics processing circuitry configured to execute instructions stored on the memory device, wherein the graphics processing circuitry is configurable to be partitioned into a plurality of isolated device partitions, each of the plurality of isolated device partitions having an independent reset and power management domain configured for fault isolation and independent concurrent execution of a workload of a plurality of workloads associated with a plurality of clients, a system interface is configured to present each of the plurality of isolated device partitions as a virtual function, wherein the graphics processing circuitry is configured to enable independent performance profiling for each of the plurality of isolated device partitions, and profiling data for an isolated device partition is accessible via a virtual function unit associated with the isolated device partition.
10 . The data processing system as in claim 9 , wherein each isolated device partition includes an independent media engine.
11 . The data processing system as in claim 9 , wherein the graphics processing circuitry includes a plurality of graphics processor cores, or a plurality of graphics processor core clusters, and the system interface is configured to:
present a first virtual function associated with a first isolated device partition; and
present a second virtual function associated with a second isolated device partition.
12 . The data processing system as in claim 11 , wherein the first isolated device partition includes a first microcontroller that includes a first scheduler to schedule workloads for execution by the first isolated device partition and the second isolated device partition includes a second microcontroller that includes a second scheduler to schedule workloads for execution by the second isolated device partition.
13 . The data processing system as in claim 12 , additionally including a plurality of hardware tiles, each hardware tile including a portion of the graphics processing circuitry, wherein the plurality of hardware tiles includes a first hardware tile associated with a first virtual function, a second hardware tile associated with a second virtual function.
14 . The data processing system as in claim 12 , additionally including a plurality of chiplets, each chiplet an at least partially packaged integrated circuit including a portion of the graphics processing circuitry, wherein the plurality of chiplets includes a first chiplet associated with a first virtual function and a second chiplet associated with a second virtual function.
15 . The data processing system as in claim 9 , wherein the graphics processing circuitry is configured to compose a composite device partition via selection, from collections of fixed function and programmable logic within the graphics processing unit, of one or more cache partitions, memory partitions, fixed function units, and compute partitions for each device partition.
16 . A method comprising:
configuring a number of cache and memory partitions for a graphics processing unit of a multi-client server device, wherein the graphics processing unit is partitionable into a plurality of isolated device partitions, each of the plurality of isolated device partitions having an independent reset and power management domain configured for fault isolation and independent workload execution;
configuring a number of compute partitions for the graphics processing unit;
compositing isolated device partitions of the graphics processing unit via selection, from collections of fixed function and programmable logic within the graphics processing unit, of one or more cache partitions, memory partitions, fixed function units, and compute partitions for each device partition;
partitioning memory bandwidth among the isolated device partitions;
configuring capabilities for the isolated device partitions, wherein configuring the capabilities for the isolated device partitions includes configuring render and media processing capabilities for the isolated device partitions based on selected fixed function units; and
executing multiple workloads in parallel from multiple clients of the multi-client server device via multiple isolated device partitions of the graphics processing unit, the multiple workloads executed according to configured capabilities of the isolated device partitions.
17 . The method as in claim 16 , wherein the graphics processing unit includes graphics processing circuitry and configuring the number of compute partitions for the graphics processing unit includes dividing the graphics processing circuitry into two or more partitions.
18 . The method as in claim 17 , wherein the graphics processing circuitry includes a plurality of graphics processor cores or a plurality of graphics processor core clusters.
19 . The method as in claim 16 , wherein configuring the render and media processing capabilities for the isolated device partitions includes configuring two or more isolated device partitions with a media processing capability.
20 . The method as in claim 19 , wherein configuring the render and media processing capabilities for the isolated device partitions includes configuring each isolated device partition with media processing capability.
21 . The method as in claim 19 , wherein configuring the render and media processing capabilities for the isolated device partitions includes configuring two or more isolated device partitions with a capability to perform operations associated with a three-dimensional (3D) rendering application programming interface (API).
22 . The method as in claim 16 , further comprising configuring independent performance profiling for the isolated device partitions of the graphics processing unit, wherein profiling data for an isolated device partition is accessible via a virtual function unit associated with the isolated device partition.