Semiconductor devices including a clock divider related to the generation of a command
A semiconductor device includes a clock division circuit configured to generate division clocks from a clock signal, based on a division enable signal that is activated based on a chip selection signal, and a valid time determination circuit configured to generate a valid signal for setting a generation time of a command, based on the chip selection signal and the division clocks.
1 . A semiconductor device comprising:
a clock division circuit configured to receive a division enable signal to generate division clocks from a clock signal, when the division enable signal is activated based on a chip selection signal; and
a valid time determination circuit configured to be electrically connected to the clock division circuit to generate a valid signal for setting a generation time of a command, based on the chip selection signal and the division clocks,
wherein the valid time determination circuit is configured to detect a logic level of the chip selection signal in synchronization with one of the division clocks to generate the valid signal, and
wherein the valid time determination circuit is configured to generate the valid signal that is activated at a valid command generation time when a detection condition of receiving the chip selection signal set to have a preset logic level in synchronization, at least two times, with one of the division clocks is satisfied.
2 . The semiconductor device of claim 1 , wherein the clock division circuit is configured to generate the division clocks when the chip selection signal is received in a preset state and the division enable signal is activated after exiting from a power-down section.
3 . The semiconductor device of claim 1 , wherein the clock division circuit is configured to generate the division clocks when the chip selection signal set to have a preset logic level is received in synchronization with the clock signal and the division enable signal is activated after exiting from a power-down section.
4 . The semiconductor device of claim 1 , wherein the valid time determination circuit is configured to generate the valid signal that is activated at a valid command generation time when a detection condition of receiving the chip selection signal set to have a preset logic level in synchronization with one of the division clocks is satisfied.
5 . The semiconductor device of claim 4 , wherein the valid time determination circuit is configured to generate the valid signal that is activated at the valid command generation time set as a time when the detection condition is satisfied or when a preset delay section elapses from the time when the detection condition is satisfied.
6 . The semiconductor device of claim 1 , wherein the valid time determination circuit is configured to generate the valid signal that is activated at a valid command generation time when the detection condition of receiving the chip selection signal set to have a preset logic level in synchronization with one of the division clocks is satisfied.
7 . The semiconductor device of claim 1 , further comprising:
a command address latch circuit configured to latch a command address in synchronization with the division clocks to generate a latch command address; and
a command address decoder configured to decode the latch command address, based on the valid signal to generate internal commands and internal addresses.
8 . The semiconductor device of claim 1 , further comprising a latency shifting circuit configured to shift an internal command in synchronization with one of the division clocks to generate a shifting command.
9 . A semiconductor device comprising:
a division enable signal generation circuit configured to generate a division enable signal that is activated when a chip selection signal set to have a preset logic level is received in synchronization with a clock signal after exiting from a power-down section; and
a valid time determination circuit configured to be electrically connected to the clock division circuit to generate a valid signal for setting a generation time of a command, based on division clocks generated based on the division enable signal and the chip selection signal,
wherein the valid time determination circuit is configured to generate the valid signal that is activated at a valid command generation time when a detection condition of receiving the chip selection signal set to have a preset logic level in synchronization, at least two times, with one of the division clocks is satisfied.
10 . The semiconductor device of claim 9 , wherein the valid time determination circuit is configured to generate the valid signal that is activated at a valid command generation time when a detection condition of receiving the chip selection signal set to have a preset logic level in synchronization with one of the division clocks is satisfied.
11 . The semiconductor device of claim 10 , wherein the valid time determination circuit is configured to generate the valid signal that is activated at the valid command generation time set as a time when the detection condition is satisfied or when a preset delay section elapses from the time when the detection condition is satisfied.
12 . The semiconductor device of claim 9 , wherein the valid time determination circuit is configured to generate the valid signal that is activated at a valid command generation time when the detection condition of receiving the chip selection signal set to have a preset logic level in synchronization with a rising edge and a falling edge of one of the division clocks is satisfied.
13 . The semiconductor device of claim 9 , further comprising:
a command address latch circuit configured to latch a command address in synchronization with the division clocks to generate a latch command address;
a command address decoder configured to decode the latch command address, based on the valid signal to generate internal commands and internal addresses; and
a latency shifting circuit configured to shift the internal command in synchronization with one of the division clocks to generate a shifting command.
14 . A semiconductor device comprising:
a clock division circuit configured to receive a division enable signal to generate division clocks from a clock signal, when the division enable signal is activated based on a chip selection signal; and
a valid time determination circuit configured to be electrically connected to the clock division circuit to generate a first valid signal and a second valid signal for setting a generation time of a command, based on the chip selection signal and the division clocks,
wherein the valid time determination circuit is configured to generate the first valid signal that is activated at a first valid command generation time and generate the second valid signal that is activated at a second valid command generation time when a detection condition of receiving the chip selection signal set to have a preset logic level in synchronization with one of the division clocks is satisfied,
wherein the valid time determination circuit is configured to generate the second valid signal that is activated at the second valid command generation time set as a time after the first valid command generation time.
15 . The semiconductor device of claim 14 , wherein the valid time determination circuit is configured to generate the first valid signal that is activated at the first valid command generation time set as a time when the detection condition is satisfied or when a preset delay section elapses from the time when the detection condition is satisfied.
16 . The semiconductor device of claim 14 , wherein the valid time determination circuit is configured to generate the first valid signal that is activated at a first valid command generation time and generate the second valid signal that is activated at a second valid command generation time when a detection condition of receiving the chip selection signal set to have a preset logic level in synchronization, at least two times, with one of the divided clocks is satisfied.