Multiple frequency range positioning signal processing

1 . An apparatus comprising:

a receiver configured to obtain, wirelessly, a first positioning signal in a first frequency range, and configured to obtain, wirelessly, a second positioning signal in a second frequency range;

a clock configured to provide a clock signal;

a first receive chain, communicatively coupled to the clock and to the receiver, comprising a first analog-to-digital converter (ADC) and configured to cause the first ADC to produce a first digital signal, based on the first positioning signal, at a first sampling rate that is based on the clock signal; and

a second receive chain, communicatively coupled to the clock and to the receiver, comprising a second ADC and configured to cause the second ADC to produce a second digital signal, based on the second positioning signal, at a second sampling rate that is based on the clock signal and that is different from, and related to, the first sampling rate; and

wherein the first receive chain and the second receive chain are configured to provide synchronized digital signals.

2 . The apparatus of claim 1 , wherein the second receive chain comprises a sampling adjustment circuit communicatively coupled to an output of the second ADC and configured to sample the second digital signal such that a first reference signal in the first receive chain downstream from the first ADC will be synchronized with a second reference signal in the second receive chain downstream from the sampling adjustment circuit.

3 . The apparatus of claim 1 , wherein the first sampling rate is 1/M times a frequency of the clock signal, wherein M is a non-zero integer, wherein the second sampling rate is 1/N times the frequency of the clock signal, wherein N is a non-zero integer, and wherein the second receive chain comprises a sampling circuit communicatively coupled to an output of the second ADC and configured to sample an input signal received by the sampling circuit at a rate of M/N times the first sampling rate.

4 . The apparatus of claim 1 , wherein the first sampling rate is 1/M times a frequency of the clock signal, wherein M is a non-zero integer, wherein the second sampling rate is 1/N times the frequency of the clock signal, wherein N is a non-zero integer, wherein the first receive chain comprises a first decimator communicatively coupled to a first output of the first ADC and configured to decimate a first input signal received by the first decimator by a factor of N, and wherein the second receive chain comprises a second decimator communicatively coupled to a second output of the second ADC and configured to decimate a second input signal received by the second decimator by a factor of M.

5 . The apparatus of claim 1 , further comprising a processor communicatively coupled to the first receive chain and the second receive chain, and configured to determine a position estimate of the apparatus based on a relationship between the first sampling rate and the second sampling rate, wherein:

the first sampling rate is 1/M times a frequency of the clock signal, wherein M is a non-zero integer;

the second sampling rate is 1/N times the frequency of the clock signal, wherein N is a non-zero integer;

the first ADC is configured to sample the first positioning signal at first sample times comprising a first set of first sample times and a second set of first sample times;

the second ADC is configured to sample the second positioning signal at second sample times comprising a first set of second sample times and a second set of second sample times;

the first set of first sample times and the first set of second sample times both correspond to a first set of L cycles of the clock signal, L being a least common denominator of 1/M and 1/N;

the second set of first sample times and the second set of second sample times both correspond to a second set of L cycles of the clock signal; and

an i th one of the first sample times of the first set of first sample times and an i th one of the first sample times of the second set of first sample times have substantially a same sampling time difference relative to a j th one of the second sample times of the first set of second sample times and a j th one of the second sample times of the second set of second sample times, respectively.

6 . The apparatus of claim 5 , wherein the processor is configured to determine the position estimate of the apparatus based on a difference between the first sampling rate and the second sampling rate.

7 . The apparatus of claim 1 , wherein the second receive chain is configured to selectively cause the second ADC to sample the second positioning signal at the second sampling rate or at the first sampling rate.

8 . The apparatus of claim 7 , wherein the second receive chain comprises a first frequency converter and a second frequency converter, and wherein the second receive chain is configured to communicatively couple the second frequency converter, while bypassing the first frequency converter, to an output of the second ADC corresponding to the second receive chain while causing the second ADC to sample the second positioning signal at the first sampling rate, and to communicatively couple the first frequency converter and the second frequency converter, in series, to the output of the second ADC corresponding to the second receive chain while causing the second ADC to sample the second positioning signal at the second sampling rate.

9 . The apparatus of claim 7 , wherein the second receive chain comprises one or more pre-processing circuits each comprising a respective pre-processing circuit frequency converter, the second receive chain comprises a plurality of baseband processing circuits each comprising a respective baseband processing circuit frequency converter, and the apparatus further comprises a multiplexer configured to selectively communicatively couple one of the plurality of baseband processing circuits to one of the one or more pre-processing circuits or to the second ADC while bypassing the one or more pre-processing circuits.

10 . The apparatus of claim 7 , wherein the second receive chain comprises a pre-processing circuit and a baseband processing circuit, the pre-processing circuit comprises a first frequency converter, a second frequency converter, and a decimator selectively coupled to one of the first frequency converter or the second frequency converter, and wherein the first frequency converter is configured to adjust a frequency of an input signal by one-fourth of a reference frequency.

11 . The apparatus of claim 1 , wherein a first integer multiple of the first sampling rate equals a second integer multiple of the second sampling rate.

12 . A positioning signal processing method comprising:

receiving, wirelessly at an apparatus, a first positioning signal in a first frequency range;

receiving, wirelessly at the apparatus, a second positioning signal in a second frequency range;

converting the first positioning signal by a first analog-to-digital converter (ADC) of the apparatus to produce a first digital signal at a first sampling rate that is based on a clock signal;

converting the second positioning signal by a second ADC of the apparatus to produce a second digital signal at a second sampling rate that is based on the clock signal and that is different from, and related to, the first sampling rate; and

adjusting at least one of the first digital signal and the second digital signal to provide synchronized digital signals.

13 . The positioning signal processing method of claim 12 , further comprising sampling the second digital signal, wherein the first digital signal will be synchronized with the second digital signal downstream from the sampling of the second digital signal.

14 . The positioning signal processing method of claim 12 , wherein the first sampling rate is 1/M times a frequency of the clock signal, wherein M is a non-zero integer, wherein the second sampling rate is 1/N times the frequency of the clock signal, wherein N is a non-zero integer, and wherein the method further comprises sampling the second digital signal at a rate of M/N times the first sampling rate.

15 . The positioning signal processing method of claim 12 , wherein the first sampling rate is 1/M times a frequency of the clock signal, wherein M is a non-zero integer, wherein the second sampling rate is 1/N times the frequency of the clock signal, wherein N is a non-zero integer, and wherein the method further comprises:

decimating the first digital signal by a factor of N; and

decimating the second digital signal by a factor of M.

16 . The positioning signal processing method of claim 12 , further comprising determining a position estimate of the apparatus based on a relationship between the first sampling rate and the second sampling rate, wherein:

the first sampling rate is 1/M times a frequency of the clock signal, wherein M is a non-zero integer;

the second sampling rate is 1/N times the frequency of the clock signal, wherein N is a non-zero integer;

the first ADC is configured to sample the first positioning signal at first sample times comprising a first set of first sample times and a second set of first sample times;

the second ADC is configured to sample the second positioning signal at second sample times comprising a first set of second sample times and a second set of second sample times;

the first set of first sample times and the first set of second sample times both correspond to a first set of L cycles of the clock signal, L being a least common denominator of 1/M and 1/N;

the second set of first sample times and the second set of second sample times both correspond to a second set of L cycles of the clock signal; and

an i th one of the first sample times of the first set of first sample times and an i th one of the first sample times of the second set of first sample times have substantially a same sampling time difference relative to a j th one of the second sample times of the first set of second sample times and a j th one of the second sample times of the second set of second sample times, respectively.

17 . The positioning signal processing method of claim 16 , wherein determining the position estimate of the apparatus comprises determining the position estimate of the apparatus based on a difference between the first sampling rate and the second sampling rate.

18 . The positioning signal processing method of claim 12 , further comprising:

receiving, wirelessly at the apparatus, a third positioning signal in the second frequency range; and

converting the third positioning signal by the second ADC of the apparatus to a third digital signal at the first sampling rate.

19 . The positioning signal processing method of claim 18 , further comprising at least one of:

applying a first decimation to the second digital signal; or

bypassing the first decimation for the third digital signal.

20 . The positioning signal processing method of claim 18 , further comprising selectively processing the second digital signal by one of a plurality of baseband processing circuits.

21 . The positioning signal processing method of claim 18 , further comprising: adjusting a frequency of the second digital signal by one-fourth of a reference frequency to produce a quarter-converted signal.

22 . The positioning signal processing method of claim 12 , wherein a first integer multiple of the first sampling rate equals a second integer multiple of the second sampling rate.

23 . An apparatus comprising:

means for receiving, wirelessly, a first positioning signal in a first frequency range;

means for receiving, wirelessly, a second positioning signal in a second frequency range;

means for converting the first positioning signal by a first analog-to-digital converter (ADC) of the apparatus to produce a first digital signal at a first sampling rate that is based on a clock signal;

means for converting the second positioning signal by a second ADC of the apparatus to produce a second digital signal at a second sampling rate that is based on the clock signal and that is different from, and related to, the first sampling rate; and

means for adjusting at least one of the first digital signal and the second digital signal to provide synchronized digital signals.

24 . The apparatus of claim 23 , further comprising means for sampling the second digital signal, wherein the first digital signal will be synchronized with the second digital signal downstream from the means for sampling the second digital signal.

25 . The apparatus of claim 23 , wherein the first sampling rate is 1/M times a frequency of the clock signal, wherein M is a non-zero integer, wherein the second sampling rate is 1/N times the frequency of the clock signal, wherein N is a non-zero integer, and wherein the apparatus further comprises means for sampling the second digital signal at a rate of M/N times the first sampling rate.

26 . The apparatus of claim 23 , wherein the first sampling rate is 1/M times a frequency of the clock signal, wherein M is a non-zero integer, wherein the second sampling rate is 1/N times the frequency of the clock signal, wherein N is a non-zero integer, and wherein the apparatus further comprises:

means for decimating the first digital signal by a factor of N; and

means for decimating the second digital signal by a factor of M.

27 . The apparatus of claim 23 , further comprising means for determining a position estimate of the apparatus based on a relationship between the first sampling rate and the second sampling rate, wherein:

the first sampling rate is 1/M times a frequency of the clock signal, wherein M is a non-zero integer;

the second sampling rate is 1/N times the frequency of the clock signal, wherein N is a non-zero integer;

the first ADC is configured to sample the first positioning signal at first sample times comprising a first set of first sample times and a second set of first sample times;

the second ADC is configured to sample the second positioning signal at second sample times comprising a first set of second sample times and a second set of second sample times;

the first set of first sample times and the first set of second sample times both correspond to a first set of L cycles of the clock signal, L being a least common denominator of 1/M and 1/N;

the second set of first sample times and the second set of second sample times both correspond to a second set of L cycles of the clock signal; and

an i th one of the first sample times of the first set of first sample times and an i th one of the first sample times of the second set of first sample times have substantially a same sampling time difference relative to a j th one of the second sample times of the first set of second sample times and a j th one of the second sample times of the second set of second sample times, respectively.