Semiconductor device and manufacturing method of semiconductor device
A semiconductor device may include a gate structure including a first conductive layer, a second conductive layer, and a third conductive layer, the third conductive layer being disposed between the first conductive layer and the second conductive layer and thicker than the first conductive layer and the second conductive layer, channel structures passing through the gate structure, and an isolation structure including a first portion passing through the second conductive layer and extended into the channel structures and a second portion protruding from the first portion into the third conductive layer and disposed between the channel structures.
1 . A semiconductor device comprising:
a gate structure including a first conductive layer, a second conductive layer, and a third conductive layer, the third conductive layer being disposed between the first conductive layer and the second conductive layer and thicker than the first conductive layer and the second conductive layer;
channel structures passing through the gate structure; and
an isolation structure including a first portion passing through the second conductive layer and extended into the channel structures and a second portion protruding from the first portion into the third conductive layer and disposed between neighboring channel structures.
2 . The semiconductor device of claim 1 , wherein the isolation structure passes through the third conductive layer.
3 . The semiconductor device of claim 1 , wherein the isolation structure comprises:
an insulating pattern passing through the second conductive layer and the third conductive layer; and
an insulating spacer disposed between the insulating pattern and the channel structure.
4 . The semiconductor device of claim 3 , wherein the insulating spacer surrounds etched surfaces of the channel structures.
5 . The semiconductor device of claim 1 , wherein the second portion has a narrower width than the first portion.
6 . The semiconductor device of claim 1 , wherein the second portion has a wider width than the first portion at a boundary of the first portion and the second portion.
7 . The semiconductor device of claim 1 , wherein, in the isolation structure, a sidewall of the first portion has a first inclination and a sidewall of the second portion has a second inclination different from the first inclination.
8 . The semiconductor device of claim 1 , wherein a bottom surface of the second portion and a bottom surface of the third conductive layer are disposed on the same or substantially the same plane.
9 . The semiconductor device of claim 1 , wherein each of the channel structures comprises a channel layer, a memory layer surrounding a sidewall of the channel layer, and an insulating core in the channel layer, and the first portion is in contact with the channel layer or the insulating core.
10 . The semiconductor device of claim 1 , wherein the third conductive layer includes a first region having a first thickness and a second region surrounding a sidewall of the second portion and having a second thickness smaller than the first thickness.
11 . The semiconductor device of claim 1 , wherein the first conductive layer is a word line, and the second conductive layer and the third conductive layer are select lines.
12 . The semiconductor device of claim 1 , wherein the second portion protrudes from a lower surface of the first portion.
13 . A semiconductor device comprising:
a gate structure including a first conductive layer, a second conductive layer and a third conductive layer, the third conductive layer being disposed between the first conductive layer and the second conductive layer, wherein the third conductive layer is thicker than the first conductive layer and the second conductive layer;
a channel structure passing through the gate structure and including an etched surface; and
an isolation structure including an insulating pattern passing through the second conductive layer and the third conductive layer, and an insulating spacer disposed between the etched surface of the channel structure and the insulating pattern.
14 . The semiconductor device of claim 13 , wherein a bottom surface of the isolation structure and a bottom surface of the third conductive layer are disposed on the same or substantially the same plane.
15 . The semiconductor device of claim 13 , wherein the insulating pattern includes a first portion passing through the second conductive layer and extended into the channel structure and a second portion protruding from the first portion into the third conductive layer.
16 . The semiconductor device of claim 15 , wherein the second portion has a narrower width than the first portion.
17 . The semiconductor device of claim 15 , wherein the second portion has a wider width than the first portion at a boundary of the first portion and the second portion.
18 . The semiconductor device of claim 15 , wherein the third conductive layer includes a first region having a first thickness and a second region surrounding a sidewall of the second portion and having a second thickness smaller than the first thickness.
19 . The semiconductor device of claim 15 , wherein the second portion protrudes from a lower surface of the first portion.