Semiconductor device and method of forming the same
A semiconductor device includes stacked-gate structures including a plurality of cell gate patterns and insulating patterns alternately stacked on a semiconductor substrate and extending in a first direction. Active patterns and gate dielectric patterns are disposed in the stacked-gate structures. The active patterns penetrate the stacked-gate structures and are spaced apart from each other in a second direction intersecting the first direction, and the gate dielectric patterns are interposed between the cell gate patterns and the active patterns and extend onto upper and lower surfaces of the cell gate patterns. The active patterns share the cell gate patterns in the stacked-gate structures.
1. A semiconductor device comprising:
a stacked-gate structure including a plurality of cell gate patterns and insulating patterns alternately and vertically stacked on a semiconductor substrate and extending in a first direction;
active patterns penetrating the stacked-gate structure and being spaced apart from each other in a second direction intersecting the first direction; and
gate dielectric patterns interposed between the cell gate patterns and the active patterns and extending onto upper and lower surfaces of the cell gate patterns,
wherein the active patterns share the cell gate patterns in the stacked-gate structure, and
wherein, from among the active patterns, an upper width of an active pattern distal from the substrate is greater than a lower width of an active pattern at the substrate.
2. The semiconductor device of claim 1 , wherein:
the stacked-gate structure includes a pair of upper selection gate patterns extending in the first direction on an uppermost cell gate pattern, and
the pair of upper selection gate patterns is disposed so as to be spaced apart from each other in the second direction.
3. The semiconductor device of claim 2 , wherein:
one of the active patterns penetrates one of the pair of upper selection gate patterns in the second direction.
4. The semiconductor device of claim 3 , wherein a plurality of the active patterns are arranged along the first direction in the one upper selection gate pattern.
5. The semiconductor device of claim 2 , wherein:
the stacked-gate structure further includes a pair of lower selection gate patterns extending in the first direction between a lowermost cell gate pattern and the semiconductor substrate, and
the pair of lower selection gate patterns is disposed so as to be spaced apart from each other in the second direction.
6. The semiconductor device of claim 2 , further comprising another stacked-gate structure spaced apart from the stacked-gate structure in the second direction,
wherein an interval between the pair of upper selection gate patterns in one stacked gate structure is narrower than an interval between the stacked-gate structures.
7. The semiconductor device of claim 6 , further comprising common source regions in the substrate between the stacked-gate structures.
8. The semiconductor device of claim 2 , wherein the gate dielectric patterns extend onto opposing sidewalls of the pair of upper selection gate patterns.
9. A semiconductor device comprising:
a stacked-gate structure including a plurality of cell gate patterns and insulating patterns alternately and vertically stacked on a semiconductor substrate and extending in a first direction;
active patterns penetrating the stacked-gate structure and being spaced apart from each other in a second direction intersecting the first direction; and
gate dielectric patterns interposed between the cell gate patterns and the active patterns and extending onto upper and lower surfaces of the cell gate patterns,
wherein:
the active patterns share the cell gate patterns in the stacked-gate structure,
the stacked-gate structure includes a pair of upper selection gate patterns extending in the first direction on an uppermost cell gate pattern,
the pair of upper selection gate patterns is disposed so as to be spaced apart from each other in the second direction, and
sidewalls of the stacked-gate structure make an angle larger than 0° with a normal line of an upper surface of the substrate.
10. The semiconductor device of claim 9 , wherein an angle between the sidewalls of the pair of upper selection gate patterns and the normal line of the upper surface of the substrate is smaller than that between the sidewalls of the stacked-gate structure and the normal line of the upper surface of the substrate.
11. The semiconductor device of claim 1 , wherein the gate dielectric patterns include an oxide layer-nitride-layer-oxynitride layer.
12. The semiconductor device of claim 9 , wherein, from among the active patterns, an upper width of an active pattern distal from the substrate is greater than a lower width of an active pattern at the substrate.
13. A semiconductor device, comprising:
a stacked-gate structure including a plurality of cell gate patterns and insulating patterns alternately and vertically stacked on a semiconductor substrate and extending in a first direction;
active patterns penetrating the stacked-gate structure and being spaced apart from each other in a second direction intersecting the first direction; and
gate dielectric patterns interposed between the cell gate patterns and the active patterns and extending onto upper and lower surfaces of the cell gate patterns,
wherein the active patterns share the cell gate patterns in the stacked-gate structure, and
wherein a width of the cell gate patterns is greater than at least twice a width of the active patterns, in the second direction.
14. The semiconductor device of claim 9 , wherein:
one of the active patterns penetrates one of the pair of upper selection gate patterns in the second direction.
15. The semiconductor device of claim 9 , wherein a plurality of the active patterns is arranged along the first direction in the one upper selection gate pattern.
16. The semiconductor device of claim 9 , wherein:
the stacked-gate structure further includes a pair of lower selection gate patterns extending in the first direction between a lowermost cell gate pattern and the semiconductor substrate, and
the pair of lower selection gate patterns is disposed so as to be spaced apart from each other in the second direction.
17. The semiconductor device of claim 9 , further comprising another stacked-gate structure spaced apart from the stacked-gate structure in the second direction,
wherein an interval between the pair of upper selection gate patterns in one stacked gate structure is narrower than an interval between the stacked-gate structures.
18. The semiconductor device of claim 9 , further comprising common source regions in the substrate between the stacked-gate structures.
19. The semiconductor device of claim 9 , wherein the gate dielectric patterns extend onto opposing sidewalls of the pair of upper selection gate patterns.
20. The semiconductor device of claim 13 , wherein a plurality of the active patterns is arranged along the first direction in the one upper selection gate pattern.