Carrier structure
A carrier structure is provided, in which at least one positioning area is defined on a chip-placement area of a package substrate, and at least one alignment portion is disposed on the positioning area. Therefore, the precision of manufacturing the alignment portion is improved by disposing the positioning area on the chip-placement area, such that the carrier structure can provide a better alignment mechanism for the chip placement operation.
1 . A carrier structure, comprising:
a package substrate defined with a chip-placement area for a single chip having a plurality of corners, wherein a positioning area is formed at one of the corners of the chip-placement area;
a first alignment portion with a first pattern; and
a second alignment portion with a second pattern, wherein the first pattern and the second pattern are different, wherein the first alignment portion and the second alignment portion are disposed on the positioning area, wherein the first alignment portion and the second alignment portion are located at two different corners of the positioning area.
2 . The carrier structure of claim 1 , wherein the package substrate has a dielectric layer and a circuit layer disposed on the dielectric layer.
3 . The carrier structure of claim 1 , wherein a side length of the positioning area is 4% to 50% of a side length of the chip-placement area.
4 . The carrier structure of claim 3 , wherein the side length of the positioning area is ¼ of the side length of the chip-placement area.
5 . The carrier structure of claim 1 , wherein both the first alignment portion and the second alignment portion are in a form of a groove.
6 . The carrier structure of claim 1 , wherein the first pattern and the second pattern are each symmetrical patterns.
7 . The carrier structure of claim 1 , wherein the first alignment portion and the second alignment portion comprise a dummy trace formed on the chip-placement area, wherein the package substrate includes an opening formed on the chip-placement area to expose the dummy trace, and another opening formed on the chip-placement area to expose a circuit layer, wherein the circuit layer is formed on the chip-placement area and free from being electrically connected to the dummy trace, and an exposed surface of the circuit layer is used for externally connecting a conductive bump.