Hybrid LDO regulator including analog LDO regulator and digital LDO regulator
A hybrid low drop-out (LDO) regulator is provided. The hybrid LDO regulator provides current to a load block, and includes: an analog LDO regulator configured to provide a first current corresponding to an average current consumed by the load block; and a digital LDO regulator configured to provide a second current corresponding to a peak current consumed by the load block based on information indicating the peak current is consumed.
1 . A hybrid low drop-out (LDO) regulator which provides current to a load block, comprising:
an analog LDO regulator configured to provide a first current corresponding to an average current consumed by the load block; and
a digital LDO regulator configured to provide a second current corresponding to a peak current consumed by the load block based on information received from the load block indicating the peak current is consumed.
2 . The hybrid LDO regulator of claim 1 , wherein the digital LDO regulator comprises:
a pass transistor array comprising a plurality of pass transistors; and
a controller configured to control at least one of the plurality of pass transistors to turn on in synchronization with a clock signal received from the load block, wherein the clock signal toggles to indicate the peak current is consumed in the load block.
3 . The hybrid LDO regulator of claim 2 , wherein the pass transistor array further comprises a plurality of NAND gates respectively corresponding to the plurality of pass transistors, and
wherein each of the plurality of NAND gates is configured to provide an output signal to a gate of a corresponding pass transistor, from among the plurality of pass transistors, based on the clock signal and a control code.
4 . The hybrid LDO regulator of claim 3 , wherein the digital LDO regulator comprises a level shifter configured to generate the control code, and generate the control code in synchronization with the clock signal.
5 . The hybrid LDO regulator of claim 2 , wherein the digital LDO regulator further comprises a comparator configured to generate a selection signal based on a feedback voltage and a reference voltage, and
wherein the controller is further configured to control a number of transistors among the plurality of pass transistors that are turned on based on the selection signal.
6 . The hybrid LDO regulator of claim 5 , wherein the digital LDO regulator further comprises a clock generator configured to generate a comparison clock signal based on the clock signal, and
wherein the comparator further is configured to generate the selection signal in synchronization with the comparison clock signal.
7 . The hybrid LDO regulator of claim 2 , wherein the controller is further configured to control the pass transistor array to perform a coarse search operation in which at least two pass transistors among the plurality of pass transistors are turned on simultaneously.
8 . The hybrid LDO regulator of claim 7 , wherein the digital LDO regulator further comprises a comparator configured to generate a selection signal based on a feedback voltage and a reference voltage, and
wherein the controller is further configured to repeatedly perform the coarse search operation until a voltage level of the feedback voltage becomes lower than a voltage level of the reference voltage.
9 . The hybrid LDO regulator of claim 8 , wherein the controller is further configured to repeatedly perform a fine search operation in which individual pass transistors, among the plurality of pass transistors, are turned on one by one.
10 . The hybrid LDO regulator of claim 9 , wherein the controller is further configured to maintain a state of the plurality of pass transistors based on a change in a voltage level of the selection signal.
11 . The hybrid LDO regulator of claim 2 , wherein the plurality of pass transistors comprises at least one large power transistor and at least one small power transistor, and
wherein the controller is further configured to turn on the at least one large power transistor before the at least one small power transistor.
12 . The hybrid LDO regulator of claim 1 , wherein the analog LDO regulator comprises:
a voltage divider configured to generate a feedback voltage based on an output voltage at an output voltage terminal;
an amplifier configured to receive the feedback voltage and a reference voltage; and
a pass transistor connected between a power supply voltage and the voltage divider, and configured to be turned on and off based on an output of the amplifier.
13 . The hybrid LDO regulator of claim 12 , further comprising a decoupling capacitor connected to the output voltage terminal.
14 . A hybrid low drop-out (LDO) regulator comprising:
an analog LDO regulator configured to provide a first current corresponding to an average current consumed in a plurality of load blocks; and
a digital LDO regulator configured to provide a second current corresponding to a peak current consumed by a load block, from among the plurality of load blocks, consuming the peak current based on information received from the load block indicating the peak current is consumed.
15 . The hybrid LDO regulator of claim 14 , wherein the digital LDO regulator comprises:
a pass transistor array comprising a plurality of pass transistors; and
a controller configured to control at least one of the plurality of pass transistors to turn on in synchronization with a clock signal received from the load block, wherein the clock signal toggles to indicate the peak current is consumed in the load block.
16 . The hybrid LDO regulator of claim 15 , wherein the pass transistor array further comprises a plurality of NAND gates respectively corresponding to the plurality of pass transistors, and
wherein each of the plurality of NAND gates is configured to provide an output signal to a gate of a corresponding pass transistor, from among the plurality of pass transistors, based on the clock signal and a control code.
17 . The hybrid LDO regulator of claim 15 , wherein the controller is further configured to control at least two pass transistors among the plurality of pass transistors to simultaneously turn on, based on the clock signal.
18 . A user device comprising:
an application processor comprising at least one hybrid low drop-out (LDO) regulator; and
a power management integrated circuit configured to provide power to the application processor,
wherein the at least one hybrid LDO regulator comprises:
an analog LDO regulator configured to provide a first current corresponding to an average current consumed in a load block; and
a digital LDO regulator configured to provide a second current corresponding to a peak current consumed by the load block based on information received from the load block indicating the peak current is consumed.
19 . The user device of claim 18 , wherein the digital LDO regulator comprises:
a pass transistor array comprising a plurality of pass transistors; and
a controller configured to control at least one of the plurality of pass transistors to turn on in synchronization with a clock signal received from the load block, wherein the clock signal toggles to indicate the peak current is consumed in the load block.
20 . The user device of claim 19 , wherein the controller is further configured to control at least two pass transistors among the plurality of pass transistors to simultaneously turn on, based on the clock signal.