Periodic and activity-based memory management
Systems, methods, and apparatuses are provided for periodic and activity-based memory management. A memory management bank can be coupled to a memory management block, wherein the memory management bank includes a plurality of memory banks. Each memory bank of the plurality of memory banks includes an activate counter to increment responsive to the memory bank receiving an activate command and circuitry to determine whether a value of the activate counter is equal to or greater than a wear leveling threshold and perform a wear leveling operation on data stored in the memory bank responsive to determining the value of the activate counter is equal to or greater than the wear leveling threshold.
1 . An apparatus, comprising:
a memory management block, wherein the memory management block includes a memory management counter to increment responsive to a memory management bank receiving a memory management command; and
the memory management bank coupled to the memory management block, wherein:
the memory management bank includes a plurality of memory banks; and
each memory bank of the plurality of memory banks includes:
an activate counter to increment responsive to the memory bank receiving an activate command; and
circuitry to:
determine whether a value of the activate counter is equal to or greater than a wear leveling threshold;
perform a wear leveling operation on data stored in the memory bank responsive to determining the value of the activate counter is equal to or greater than the wear leveling threshold;
determine whether a value of the memory management counter is equal to or greater than a sense and flip operation threshold; and
perform a sense and flip operation on data stored in the memory bank responsive to determining the value of the memory management counter is greater than the sense and flip operation threshold.
2 . The apparatus of claim 1 , wherein an amount of power used for memory management by each memory bank of the plurality of memory banks is proportional to a quantity of activate commands received by the memory bank.
3 . The apparatus of claim 1 , wherein the memory management block is to determine whether a memory operation is performed on data stored in a memory bank of the plurality of memory banks in response to receiving a command.
4 . The apparatus of claim 3 , wherein the memory management block is to determine whether to perform the wear leveling operation on data stored in the memory bank, a sense and flip operation on the data stored in the memory bank, or no operation on the data stored in the memory bank in response to determining the memory operation has been performed on the data.
5 . A method, comprising:
determining a value of an activate flag;
performing a sense and flip operation on data stored in a memory bank in response to determining the activate flag has a first value;
comparing a value of a first counter to a value of a first threshold in response to determining the activate flag has a second value, wherein the first counter is a memory management command counter that increments responsive to the memory bank receiving a memory management command;
resetting the value of the first counter in response to determining the value of the first counter is greater than or equal to the value of the first threshold;
incrementing the value of the first counter in response to determining the value of the first counter is less than the value of the first threshold; and
performing a wear leveling operation on the data stored in the memory in response to determining a value of a second counter is greater than or equal to a value of a second threshold.
6 . The method of claim 5 , wherein the first threshold is sense and flip operation threshold.
7 . The method of claim 5 , wherein the second counter is an activate counter that increments responsive to the memory receiving an activate command.
8 . The method of claim 5 , wherein the second threshold is a wear leveling operation threshold.
9 . The method of claim 5 , further comprising resetting the value of the first counter in response to powering up the memory.
10 . The method of claim 5 further comprising resetting the value of the second counter in response to powering up the memory.
11 . The method of claim 5 , further comprising resetting the value of the activate flag in response to powering up the memory.
12 . The method of claim 5 , further comprising performing a sense and flip operation on the data stored in the memory in response to resetting the value of the first counter.
13 . The method of claim 5 , further comprising refraining from performing the wear leveling operation in response to determining the value of the second counter is less than the value of the second threshold.
14 . A system, comprising:
a host; and
a memory device coupled to the host, wherein the memory device includes:
memory management circuitry, wherein the memory management circuitry includes:
a plurality of memory banks; and
a memory management block to determine whether to perform a sense and flip operation on data stored in the plurality of memory banks, perform a wear leveling operation on the data stored in the plurality of memory banks, or perform no operation on the data stored in the plurality of memory banks; and
wherein each memory bank of the plurality of memory banks includes:
a first logic gate to couple the memory bank to the memory management block;
circuitry to perform the wear leveling operation;
an activate counter to increment responsive to the memory management circuitry receiving an activate command from the host;
circuitry to compare a value of the activate counter to a value of a wear leveling threshold; and
a second logic gate to couple the memory bank to other memory banks of the plurality of memory banks.
15 . The system of claim 14 , wherein the memory management circuitry includes a third logic gate to couple the memory management block to the first logic gate of each memory bank.
16 . The system of claim 15 , wherein the memory management circuitry is to send a wear leveling operation command to the plurality of memory banks via the third logic gate.
17 . The system of claim 14 , wherein the second logic gate of one of the memory banks of the plurality of memory banks is coupled to ground.
18 . A method, comprising:
determining a value of an activate flag;
performing a sense and flip operation on data stored in a memory bank in response to determining the activate flag has a first value;
setting the value of the activate flag to a second value in response to the memory receiving an activate command;
comparing a value of a first counter to a value of a first threshold in response to determining the activate flag has the second value;
resetting the value of the first counter in response to determining the value of the first counter is greater than or equal to the value of the first threshold;
incrementing the value of the first counter in response to determining the value of the first counter is less than the value of the first threshold; and
performing a wear leveling operation on the data stored in the memory in response to determining a value of a second counter is greater than or equal to a value of a second threshold.