Deep neural network based on flash analog flash computing array
A deep neural network based on analog FLASH computing array, includes a number of computing arrays, a number of subtractors, a number of activation circuit units and a number of integral-recognition circuit units. The computing array includes a number of computing units, a number of word lines, a number of bit lines and a number of source lines. Each of the computing units includes a FLASH cell. The gate electrodes of the FLASH cells in the same column are connected to the same word line. The source electrodes of the FLASH cells in the same column are connected to the same source line, and the drain electrodes of the FLASH cells in the same row are connected to the same bit line. Each of the subtractors includes a positive terminal, a negative terminal and an output terminal.
1 . A deep neural network based on analog FLASH computing array, comprising: a plurality of computing arrays, a plurality of subtractors, a plurality of activation circuit units and a plurality of integral-recognition circuit units; wherein each of the computing arrays comprises a plurality of computing units comprising a plurality of FLASH cells, a plurality of word lines, a plurality of bit lines and a plurality of source lines; each of the computing units comprises a FLASH cell,
wherein each of the computing arrays comprises an array of rows and columns such that the plurality of FLASH cells are arranged in the rows and the columns, and gate electrodes of the FLASH cells in the same column are connected to the same word line, source electrodes of the FLASH cells in the same column are connected to the same source line, and drain electrodes of the FLASH cells in the same row are connected to the same bit line; each of the subtractors comprises a positive terminal, a negative terminal and an output terminal, the positive terminal and the negative terminal are respectively connected to two adjacent bit lines, and the output terminal is connected to an input terminal of an activation circuit or an integral-recognition circuit,
wherein the number of the word lines corresponds to the number of columns in the computing array, and the word lines are configured to apply control signals to the gate electrodes of the FLASH cells, so as to control the FLASH cells to participate in an operation or not,
wherein the number of the source lines corresponds to the number of columns in the computing array, and the source lines are configured to apply input signals to the source electrodes of the FLASH cells, the input signals are the analog voltages representing element values of DNN input vectors, the analog voltages are arranged in a row and input to the source electrodes of the FLASH cells in each column through the corresponding source lines,
wherein the number of the bit lines corresponds to the number of rows in the computing array, the bit lines are configured to output the signals of the drain electrodes of the FLASH cells, and each of the bit lines is configured to superimpose the drain signal of the FLASH cells in one row and to output the superimposed drain signal as an output signal,
wherein the plurality of computing arrays forms convolutional layers,
wherein threshold voltages of the FLASH cells in the convolutional layers represent elements in a weight matrix, which are set by pre-programming,
wherein the convolutional layers are implemented by setting idle FLASH cells to a threshold voltage state by setting only k*k FLASH cells corresponding to a size of a convolution kernel on the two bit lines connected to each of the plurality of subtractors, and a shift operation of the convolution kernel is implemented by a relative shift of the threshold voltage arrangement between the two bit lines connected to each of the plurality of subtractors in a respective computing array.
2 . The deep neural network of claim 1 , wherein the plurality of computing array forms fully connected layers, threshold voltages of the FLASH cells represent elements in a weight matrix and are set by pre-programming.
3 . The deep neural network of claim 1 , further comprising integral-recognition circuits and activation circuits, wherein the output terminal of each of the subtractors is connected to the integral-recognition circuit or the activation circuit.
4 . The deep neural network of claim 1 , further comprising pooling layers, which achieve pooling functions by connecting the output terminals of the subtractors together.
5 . The deep neural network of claim 1 , wherein the FLASH cell comprises a floating gate memory, a split gate memory, a charge trap memory, or an embedded flash memory device.