Multi-modulus divider
A multi-modulus divider includes a prescaler and a finite state machine. The prescaler includes a combinational logic circuit programmable to divide a frequency of an input clock signal by a first value or a second value. The multi-modulus divider includes a first flip-flop having a data input coupled to an output of the prescaler and an output coupled to an input of the finite state machine. The multi-modulus divider includes a second flip-flop having a data input coupled to the finite state machine such that the data input is configured to receive a programming signal output by the finite state machine and associated with programming the combinational logic circuit. The multi-modulus divider includes a third flip-flop having a data input coupled to an output of the second flip-flop. The third-flip flop also has an output coupled to the combinational logic circuit.
1 . A multi-modulus divider comprising:
a prescaler comprising a combinational logic circuit programmable to divide a frequency of an input clock signal by a first value or a second value;
a finite state machine;
a first flip-flop, wherein a data input of the first flip-flop is coupled to an output of the prescaler, and wherein an output of the first flip-flop is coupled to an input of the finite state machine;
a second flip-flop, wherein a data input of the second flip-flop is coupled to the finite state machine such that the data input of the second flip-flop is configured to receive a programming signal output by the finite state machine and associated with programming the combinational logic circuit; and
a third flip-flop, wherein a data input of the third flip-flop is coupled to an output of the second flip-flop, and wherein an output of the third flip-flop is coupled to the combinational logic circuit.
2 . The multi-modulus divider of claim 1 , wherein a longest flop-to-flop delay is a summation of a first delay associated with the first flip-flop and a second delay associated with the second flip-flop.
3 . The multi-modulus divider of claim 1 , wherein the input clock signal has a frequency that is greater than 7 Gigahertz (GHz).
4 . The multi-modulus divider of claim 1 , wherein the first flip-flop, the second flip-flop, and the third flip-flop each comprise a delay (D) flip-flop.
5 . The multi-modulus divider of claim 1 , wherein a clock input of the first flip-flop and a clock input of the third flip-flop are configured to receive the input clock signal.
6 . The multi-modulus divider of claim 1 , wherein the finite state machine includes the second flip-flop.
7 . The multi-modulus divider of claim 1 , wherein:
the first value is a first integer, and
the second value is a second integer that is different than the first integer.
8 . The multi-modulus divider of claim 1 , wherein the prescaler further comprises a plurality of flip-flops, each of the plurality of flip-flops including a data input coupled to the combinational logic circuit and an output coupled to the combinational logic circuit.
9 . The multi-modulus divider of claim 8 , wherein the data input of the first flip-flop is coupled to the output of one of the plurality of flip-flops of the prescaler.
10 . The multi-modulus divider of claim 1 , wherein the output of the first flip-flop is coupled to a clock input of the second flip-flop.
11 . A phase-locked loop (PLL) circuit comprising the multi-modulus divider of claim 1 .