Multi-storage gated imaging system

1 . A gated imaging system, comprising:

a pulsed illuminator configured to generate a plurality of light pulses; and

a pixel circuit, comprising:

a photodiode configured to collect photogenerated image charges in response to incident light,

a floating diffusion coupled to receive the image charges from the photodiode,

a sense node amplifier coupled to the floating diffusion,

a storage network coupled between the photodiode and the floating diffusion, the storage network comprising a plurality of memory nodes coupled between the photodiode and the floating diffusion, and

a transfer transistor coupling the photodiode to each of the plurality of memory nodes,

wherein the storage network is configured to capture a plurality of depth slices between two successive ones of the light pulses.

2 . The gated imaging system of claim 1 , wherein each of the memory nodes is configured to pulse for a corresponding one of the depth slices between the two successive ones of the light pulses.

3 . The gated imaging system of claim 1 , wherein individual ones of the memory nodes comprise a transistor or a diode.

4 . The gated imaging system of claim 1 , wherein the pixel circuit further comprises a photodiode reset transistor coupled between the photodiode and a voltage source, wherein the photodiode reset transistor is configured to reset the photodiode each time the storage network captures one of the depth slices.

5 . The gated imaging system of claim 1 , wherein the pixel circuit further comprises a network reset transistor coupled between the storage network and a voltage source, wherein the network reset transistor is configured to reset the storage network at an end of a readout period.

6 . The gated imaging system of claim 1 , further comprising a readout circuit coupled to the pixel circuits and configured to read out the depth slices after the storage network captures the depth slices between two successive ones of the light pulses.

7 . The gated imaging system of claim 1 , wherein the pixel circuit is one of a plurality of pixel circuits included in a pixel array.

8 . The gated imaging system of claim 1 , wherein the floating diffusion comprises a plurality of floating diffusion portions, wherein each floating diffusion portion is coupled to at least one of the memory nodes.

9 . The gated imaging system of claim 1 , wherein the sense node amplifier comprises a source follower transistor, wherein the floating diffusion is coupled to a gate terminal of the source follower transistor.

10 . The gated imaging system of claim 1 , wherein the transfer transistor couples the photodiode directly to each of the plurality of memory nodes.

11 . The gated imaging system of claim 1 , wherein:

the floating diffusion is a first floating diffusion;

the pixel circuit further comprises a second floating diffusion different from the first floating diffusion; and

the storage network further comprises one or more second memory nodes coupled between the photodiode and the second floating diffusion.

12 . A gated imaging system, comprising:

a pulsed illuminator configured to generate a plurality of light pulses; and

a pixel circuit, comprising:

a photodiode configured to collect photogenerated image charges in response to incident light; and

a plurality of depth slice storage circuits coupled to receive the photogenerated image charges from the photodiode, each depth slice storage circuit comprising:

an independent floating diffusion coupled to receive the image charges from the photodiode;

an independent sense node amplifier coupled to the independent floating diffusion;

at least one independent memory node coupled between the photodiode and the independent floating diffusion; and

an independent row select transistor coupled to the independent sense node amplifier,

wherein the independent row select transistors of the plurality of depth slice storage circuits couple the independent sense node amplifiers to a same bitline, and

wherein the depth slice storage circuits are configured to capture a plurality of depth slices between two successive ones of the light pulses.

13 . The gated imaging system of claim 12 , wherein each independent memory node is configured to pulse for a corresponding one of the depth slices between the two successive ones of the light pulses.

14 . The gated imaging system of claim 12 , wherein each depth slice storage circuit further comprises an independent network reset transistor coupled between the independent floating diffusion and a voltage source, wherein the independent network reset transistor is configured to reset the at least one independent memory node at an end of a readout period.

15 . The gated imaging system of claim 12 , wherein the independent sense node amplifier comprises a source follower transistor, wherein the independent floating diffusion is coupled to a gate terminal of the source follower transistor.

16 . A method of operating a pixel circuit, the method comprising:

configuring a pulsed illuminator to generate a plurality of light pulses;

coupling a floating diffusion between (i) a photodiode configured to collect photogenerated image charge in response to image light and (ii) a sense node amplifier;

coupling a storage network between the photodiode and the floating diffusion, the storage network comprising:

a plurality of memory nodes coupled between the photodiode and the floating diffusion; and

configuring the storage network to capture (i) a first plurality of depth slices between a first two successive ones of the light pulses and (ii) a second two successive ones of the light pulses,

wherein the first plurality of depth slices includes a first number of depth slices, and

wherein the second plurality of depth slices includes a second number of depth slices different from the first number.

17 . The method of claim 16 , further comprising:

configuring one or more of the memory nodes to pulse for a corresponding one of the depth slices between the first two successive ones of the light pulses.

18 . The method of claim 16 , further comprising:

configuring each of the memory nodes to pulse for a corresponding one of the depth slices between the first two successive ones of the light pulses.

19 . The method of claim 16 , wherein individual ones of the memory nodes comprise a transistor or a diode.

20 . The method of claim 16 , further comprising:

coupling a photodiode reset transistor between the photodiode and a voltage source; and

configuring the photodiode reset transistor to reset the photodiode each time the storage network captures one of the depth slices.

21 . The method of claim 16 , further comprising

coupling a network reset transistor between the storage network and a voltage source; and

configuring the network reset transistor to reset the storage network at an end of a readout period.

22 . The method of claim 16 , further comprising:

coupling the pixel circuit to a readout circuit; and

configuring the readout circuit to read out the depth slices after the storage network captures the depth slices between first two successive ones of the light pulses.

23 . The method of claim 16 , wherein:

a first timing of the first plurality of depth slices between the first two successive ones of the light pulses randomly differs from a second timing of the second plurality of depth slices between the second two successive ones of the light pulses;

the second number randomly differs from the first number; or

a combination thereof.

24 . The method of claim 16 , wherein:

a first timing of the first plurality of depth slices between the first two successive ones of the light pulses differs linearly, exponentially, or in accordance with a first normal distribution from a second timing of the second plurality of depth slices between the second two successive ones of the light pulses in accordance;

the second number differs linearly, exponentially, or in accordance with a second normal distribution from the first number; or

a combination thereof.