Phase-locked loop, radar system and method for randomizing initial phases of FMCW signals
View Patent ↗Embodiments of the present disclosure disclose a phase-locked loop, a radar system and a method for randomizing initial phases of FMCW signals. The phase-locked loop includes a phase-locked loop circuit and a random control signal generator. In response to a clock signal indicating a respective target moment of one or more target moments, the random control signal generator inputs a random control signal to the phase-locked loop circuit, so that the accumulated value of the plurality of fractional frequency division values is converted into a random value, and that a plurality of phase differences respectively corresponding to the plurality of chirp signals form a non-arithmetic sequence.
1 . A phase-locked loop, comprising:
a phase-locked loop circuit, having a first input port, a second input port, and a frequency division value input port; and
a random control signal generator, including a control port configured to receive a clock signal;
wherein the phase-locked loop circuit is configured to generate a plurality of frequency-modulated continuous chirp signals;
wherein, in response to a reference signal being input at the first input port, a feedback signal being input at the second input port, a frequency division value being input at the frequency division value input port, the frequency division value having an integral part and a fractional part, the fractional part being an accumulated value of a plurality of fractional frequency division values,
the phase-locked loop circuit is configured to generate a respective chirp signal of the plurality of frequency-modulated continuous chirp signals based on the reference signal and the feedback signal, and to perform frequency division on the respective chirp signal at a frequency division ratio obtained based on the frequency division value, to generate another feedback signal that is fed back to the second input port; and
wherein there is a phase difference between a phase of a spurious signal and an initial phase of a main signal in the respective chirp signal, the spurious signal being generated in response to the respective chirp signal being subjected to instantaneous phase changes caused by variation of the frequency division value between an integer and a next integer; and
wherein in response to the clock signal reaching a target moment, the random control signal generator is configured to send a random control signal to the frequency division value input port of the phase-locked loop circuit, causing the accumulated value of the plurality of fractional frequency division values to be converted into a random value, and a plurality of phase differences respectively corresponding to the plurality of chirp signals to form a non-arithmetic sequence.
2 . The phase-locked loop according to claim 1 , wherein the target moments refers to a moments within a time period starting from an ending moment of a useful signal time period of a respective chirp signal of the plurality of chirp signals and ending at a beginning moment of a useful signal time period of a next chirp signal.
3 . The phase-locked loop according to claim 2 , wherein the random control signal includes a random sequence configured to add with or substitute the accumulated value of the plurality of fractional frequency division values, so that the accumulated value of the plurality of fractional frequency division values is converted into the random value.
4 . The phase-locked loop according to claim 3 , wherein the random sequence is added with or substitutes the accumulated value bit by bit.
5 . The phase-locked loop according to claim 1 , wherein the random control signal includes a random sequence configured to add with or substitute the accumulated value of the plurality of fractional frequency division values, so that the accumulated value of the plurality of fractional frequency division values is converted into the random value.
6 . The phase-locked loop according to claim 5 , wherein the random sequence is added with or substitutes the accumulated value bit by bit.
7 . The phase-locked loop according to claim 6 , wherein the random control signal generator includes one or more of:
a linear feedback shift register, wherein a control port of the linear feedback shift register is configured to receive a first instruction signal generated based on the clock signal, wherein the first instruction signal is configured to instruct the linear feedback shift register to operate to generate one random sequence output to the frequency division value input port of the phase-locked loop circuit, so that the accumulated value of the plurality of fractional frequency division values is converted into the random value; and
a memory, wherein a control port of the memory is configured to receive a second instruction signal generated based on the clock signal, wherein the second instruction signal is configured to instruct the memory to output one pre-stored random sequence to the frequency division value input port of the phase-locked loop circuit, so that the accumulated value of the plurality of fractional frequency division values is converted into the random value.
8 . The phase-locked loop according to claim 7 , wherein the random control signal generator further includes:
a digital waveform generator, wherein the clock signal is input at a control port of the digital waveform generator, and the digital waveform generator is configured to identify whether the clock signal indicates the target moment, and in response to the clock signal reaching the target moment, instruct one or more of the linear feedback shift register and the memory to input one random sequence to the frequency division value input port of the phase-locked loop circuit, so that the accumulated value of the plurality of fractional frequency division values is converted into the random value.
9 . The phase-locked loop according to claim 8 , wherein the digital waveform generator is further configured to, under control of the clock signal, input the frequency division value to the frequency division value input port of the phase-locked loop circuit.
10 . The phase-locked loop according to claim 5 , wherein the random control signal generator includes one or more of:
a linear feedback shift register, wherein a control port of the linear feedback shift register is configured to receive a first instruction signal generated based on the clock signal, wherein the first instruction signal is configured to instruct the linear feedback shift register to operate to generate one random sequence output to the frequency division value input port of the phase-locked loop circuit, so that the accumulated value of the plurality of fractional frequency division values is converted into the random value; and
a memory, wherein a control port of the memory is configured to receive a second instruction signal generated based on the clock signal, wherein the second instruction signal is configured to instruct the memory to output one pre-stored random sequence to the frequency division value input port of the phase-locked loop circuit, so that the accumulated value of the plurality of fractional frequency division values is converted into the random value.
11 . The phase-locked loop according to claim 10 , wherein the random control signal generator further includes:
a digital waveform generator, wherein the clock signal is input at a control port of the digital waveform generator, and the digital waveform generator is configured to identify whether the clock signal indicates the target moment, and in response to the clock signal reaching the target moment, instruct one or more of the linear feedback shift register and the memory to input one random sequence to the frequency division value input port of the phase-locked loop circuit, so that the accumulated value of the plurality of fractional frequency division values is converted into the random value.
12 . The phase-locked loop according to claim 11 , wherein the digital waveform generator is further configured to, under control of the clock signal, input the frequency division value to the frequency division value input port of the phase-locked loop circuit.
13 . The phase-locked loop according to claim 1 , wherein the frequency division value input port includes a third input port and a fourth input port; and the phase-locked loop circuit further includes:
a phase frequency detector, a charge pump, a low-pass filter, a voltage-controlled oscillator and a frequency division module electrically connected in sequence to form a loop;
wherein a first input port of the phase frequency detector is connected to the first input port of the phase-locked loop circuit, a second input port of the phase frequency detector is connected to the second input port of the phase-locked loop circuit, a first input port of the frequency division module is connected to the third input port of the phase-locked loop circuit, a second input port of the frequency division module is connected to the fourth input port of the phase-locked loop circuit, and an output port of the voltage-controlled oscillator is connected to an output port of the phase-locked loop circuit;
wherein the phase frequency detector is configured to detect a phase difference between the reference signal and the feedback signal, and generate a plurality of phase error signals, wherein the plurality of phase error signals are converted into a voltage control signal by the charge pump and the low-pass filter, and the voltage control signal is configured to control the voltage-controlled oscillator to output the respective chirp signal of the plurality of frequency-modulated continuous chirp signals, and wherein the frequency division module is configured to accumulate the plurality of fractional frequency division values, and perform frequency division on the respective chirp signal of the plurality of chirp signals at the frequency division ratio obtained based on the accumulated value of the plurality of fractional frequency division values and on the integral frequency division value input at the first input port of the frequency division module, to generate the another feedback signal that is fed back to the second input port of the phase frequency detector, wherein the phase-locked loop circuit maintains a locked status by maintaining frequency and a phase of the feedback signal to be same as frequency and a phase of the reference signal; and
wherein the frequency division module is further configured to receive the random control signal at the second input port of the frequency division module, so that the frequency division module converts, under control of the random control signal, the accumulated value of the plurality of fractional frequency division values into the random value.
14 . The phase-locked loop according to claim 13 , wherein the frequency division module includes a frequency divider and a modulator;
wherein the clock signal is input at a control port of the modulator, a first input port of the modulator is connected to the first input port of the frequency division module, and a second input port of the modulator is connected to the second input port of the frequency division module, and wherein the modulator is configured to, under control of the clock signal, accumulate the plurality of fractional frequency division values input at the second input port of the modulator, and generate, based on the accumulated value of the plurality of fractional frequency division values and the integral frequency division value input at the first input port of the modulator, a frequency division ratio control signal and output the frequency division ratio control signal to the frequency divider;
wherein the frequency division ratio control signal is received at a control port of the frequency divider, an input port of the frequency divider is connected to the output port of the voltage-controlled oscillator, and an output port of the frequency divider is connected to the second input port of the phase frequency detector, and wherein the frequency divider is configured to, under control of the frequency division ratio control signal, perform frequency division on the respective chirp signal of the plurality of chirp signals output by the voltage-controlled oscillator at the frequency division ratio, and generate the another feedback signal that is fed back to the second input port of the phase frequency detector; and
wherein the modulator is further configured to receive the random control signal at the second input port of the modulator, and convert, under control of the random control signal, the accumulated value of the plurality of fractional frequency division values into the random value.
15 . The phase-locked loop according to claim 1 , wherein the spurious signal is generated by mixing the feedback signal generated by the frequency division with the reference signal input to the phase-locked loop.
16 . A radar system, comprising the phase-locked loop according to claim 1 , wherein the phase-locked loop is configured to generate a plurality of frequency-modulated continuous chirp signals.
17 . A method for randomizing an initial phase of a frequency-modulated continuous wave (FMCW) signal, applicable to a phase-locked loop including a phase-locked loop circuit, the method comprises:
receiving a reference signal and a feedback signal at the phase-locked loop circuit;
generating, by the phase-locked loop circuit, a respective chirp signal of a plurality of frequency-modulated continuous chirp signals, wherein there is a phase difference between a phase of a spurious signal and an initial phase of a main signal in the respective chirp signal of the plurality of chirp signals, the spurious signal being generated in response to the respective chirp signal of the plurality of chirp signals being subjected to instantaneous phase changes caused by variation of a frequency division value between an integer and a next integer, the frequency division value including an integer part and a fractional part, the fractional part being an accumulated value of a plurality of fractional frequency division values;
receiving the frequency division value;
performing, by the phase-locked loop circuit, frequency division on the plurality of chirp signals at a frequency division ratio obtained based on the frequency division value; and
randomizing the accumulated value, such that a plurality of phase differences respectively corresponding to the plurality of chirp signals form a non-arithmetic sequence, in response to receiving a random control signal at the phase-locked loop circuit at a target moment.
18 . The method according to claim 17 , wherein the target moments are is determined based on the feedback signal.
19 . The method according to claim 17 , wherein the random control signal includes a random sequence, and receiving the random control signal at the phase-locked loop circuit at the target moment, to randomize the accumulated value of the plurality of fractional frequency division values, includes:
receiving the random sequence at the phase-locked loop circuit at the target moment; and
adding the random sequence with the accumulated value of the plurality of fractional frequency division values, or substituting the accumulated value of the plurality of fractional frequency division values with the random sequence, so that the accumulated value of the plurality of fractional frequency division values is converted into the random value.
20 . The method according to claim 19 , wherein adding the random sequence with the accumulated value of the plurality of fractional frequency division values, includes:
adding, from high-order bits to low-order bits of the accumulated value, the random sequence with the accumulated value of the plurality of fractional frequency division values bit by bit; or
substituting the accumulated value of the plurality of fractional frequency division values with the random sequence, includes:
substituting, from high-order bits to low-order bits of the accumulated value, the accumulated value of the plurality of fractional frequency division values with the random sequence bit by bit.